參數(shù)資料
型號(hào)： PPC405GPR-3BB266
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GPr Embedded Processor
中文描述： 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, EBGA-456
文件頁數(shù)： 31/57頁
文件大?。?/td> 614K
代理商： PPC405GPR-3BB266
405GPr – Power PC 405GPr Embedded Processor
AMCC
31
Revision 2.04 – September 7, 2007
Data Sheet
PCIGnt0[Req]
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
O
5V tolerant
3.3V PCI
PCIGnt1:5
Used as PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
Ethernet Interface
PHYRxD3:0
Received data. This is a nibble wide bus from the PHY. The data is
synchronous with the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
EMCTxD3:0
Transmit data. A nibble wide data bus towards the net. The data is
synchronous to the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYRxErr
Receive Error. This signal comes from the PHY and is synchronous
to the PHYRxClk.
I
5V tolerant
3.3V LVTTL
1
PHYRxClk
Receiver Medium clock. This signal is generated by the PHY.
I
5V tolerant
3.3V LVTTL
1
PHYRxDV
Receive Data Valid. Data on the Data Bus is valid when this signal is
activated. Deassertion of this signal indicates end of the frame
reception.
I
5V tolerant
3.3V LVTTL
1
PHYCrS
Carrier Sense signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMCTxErr
Transmit Error. This signal is generated by the Ethernet controller, is
connected to the PHY and is synchronous with the PHYTxClk. It
informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
6
EMCTxEn
Transmit Enable. This signal is driven by the EMAC to the PHY. Data
is valid during the active state of this signal. Deassertion of this signal
indicates end of frame transmission. This signal is synchronous to
the PHYTxClk.
O
5V tolerant
3.3V LVTTL
6
PHYTxClk
This clock comes from the PHY and is the Medium Transmit clock.
I
5V tolerant
3.3V LVTTL
1
PHYCol
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMCMDClk
Management Data Clock. The MDClk is sourced to the PHY. This
clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC].
Management information is transferred synchronously with respect to
this clock.
O
5V tolerant
3.3V LVTTL
EMCMDIO[PHYMDIO]
Management Data Input/Output is a bidirectional signal between the
Ethernet controller and the PHY. It is used to transfer control and
status information.
I/O
5V tolerant
3.3V LVTTL
1
Signal Functional Description
(Sheet 2 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
PPC405GPR-3BB266Z Power PC 405GPr Embedded Processor
PPC405GPR-3BB333 Power PC 405GPr Embedded Processor
PPC405GPR-3BB333Z Power PC 405GPr Embedded Processor
PPC405GPR-3BB400 Power PC 405GPr Embedded Processor
PPC405GPR-3BB400Z Power PC 405GPr Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GPR-3BB266Z 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 266MHz 3.3V 456-Pin EBGA T/R
PPC405GPR-3BB333 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 333MHz 3.3V 456-Pin EBGA Tray
PPC405GPR-3BB333Z 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 333MHz 3.3V 456-Pin EBGA T/R
PPC405GPR-3BB400 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 400MHz 3.3V 456-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405GPR RISC 32BIT 0.18UM 400MHZ 3.3V 456PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405GPR-3BB400 CPU PERFORMANCESRAM
PPC405GPR-3BB400Z 制造商:AppliedMicro 功能描述:MPU 405GPr RISC 32-Bit 0.18um 400MHz 3.3V 456-Pin EBGA T/R 制造商:AMCC 功能描述:AMCPPC405GPR-3BB400Z CPU EOL090410
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