參數(shù)資料
型號： PPC405GP-3FE266C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GP Embedded Processor
中文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, LEAD FREE, EBGA-456
文件頁數(shù)： 49/59頁
文件大?。?/td> 782K
代理商： PPC405GP-3FE266C
405GP – Power PC 405GP Embedded Processor
AMCC
49
Revision 2.03 – September 7, 2007
Data Sheet
Peripheral Interface Clock Timings
Parameter
Min
Note 1
15
25
30
Max
66.66
Note 1
33.33
40
Units
MHz
ns
MHz
ns
ns
ns
MHz
ns
ns
ns
MHz
ns
ns
ns
MHz
ns
ns
ns
MHz
ns
MHz
ns
MHz
ns
ns
ns
ns
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
PCIClk input low time
EMCMDClk output frequency
EMCMDClk period
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
PHYTxClk period
PHYTxClk input high time
PHYTxClk input low time
PHYRxClk input frequency
PHYRxClk period
PHYRxClk input high time
PHYRxClk input low time
PerClk output frequency–133MHz
PerClk period–133MHz
PerClk output frequency–200MHz
PerClk period–200MHz
PerClk output frequency–266MHz
PerClk period–266MHz
PerClk output high time
PerClk output low time
PerClk clock edge stability (phase jitter, cycle to cycle)
40% of nominal period
40% of nominal period
–
400
160
160
2.5
40
35% of nominal period
35% of nominal period
2.5
40
35% of nominal period
35% of nominal period
–
30
–
20
–
15
45% of nominal period
45% of nominal period
60% of nominal period
60% of nominal period
2.5
–
–
–
25
400
–
–
25
400
–
–
33.33
–
50
–
66.66
–
55% of nominal period
55% of nominal period
± 0.3
1000/(2T
OPB
+2ns)
UARTSerClk input frequency
(Note 3)
–
MHz
UARTSerClk period
2T
OPB
+2
T
OPB
+1
T
OPB
+1
–
30
–
20
–
15
–
ns
UARTSerClk input high time
–
ns
UARTSerClk input low time
–
ns
TmrClk input frequency–133MHz
TmrClk period–133MHz
TmrClk input frequency–200MHz
TmrClk period–200MHz
TmrClk input frequency–266MHz
TmrClk period–266MHz
TmrClk input high time
TmrClk input low time
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the
PowerPC 405GP Embedded Processor
User’s Manual
for more information.
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T
OPB
is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for 266MHz
parts.
33.33
–
50
–
66.66
–
MHz
ns
MHz
ns
MHz
ns
ns
ns
40% of nominal period
40% of nominal period
60% of nominal period
60% of nominal period
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3FE266CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA T/R
PPC405GP-3KE133C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3KE133CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3KE200C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray
PPC405GP-3KE200CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
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