參數(shù)資料
型號(hào)： PPC405GP-3FE133C
廠商： APPLIEDMICRO INC
元件分類(lèi)： 微控制器/微處理器
英文描述： Power PC 405GP Embedded Processor
中文描述： 32-BIT, 133 MHz, RISC PROCESSOR, PBGA456
封裝： 35 X 35 MM, PLASTIC, LEAD FREE, EBGA-456
文件頁(yè)數(shù)： 40/59頁(yè)
文件大?。?/td> 782K
代理商： PPC405GP-3FE133C
405GP – Power PC 405GP Embedded Processor
40
AMCC
Revision 2.03 – September 7, 2007
Data Sheet
UART1_Tx
UART1 Serial Data Out.
O
5V tolerant
3.3V LVTTL
6
UART1_DSR/
UART1_CTS
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR bit.
I
5V tolerant
3.3V LVTTL
1
UART1_RTS/
UART1_DTR
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
6
IICSCL
IIC Serial Clock.
I/O
5V tolerant
3.3V LVTTL
1, 2
IICSDA
IIC Serial Data.
I/O
5V tolerant
3.3V LVTTL
1, 2
Interrupts Interface
IRQ0:6[GPIO17:23]
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
I[I/O]
5V tolerant
3.3V LVTTL
1
JTAG Interface
TDI
Test data in.
I
5V tolerant
3.3V LVTTL
1, 4
TMS
JTAG test mode select.
I
5V tolerant
3.3V LVTTL
1, 4
TDO
Test data out.
O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GP.
I
5V tolerant
3.3V LVTTL
5
System Interface
SysClk
Main system clock input.
I
5V tolerant
3.3V LVTTL
SysReset
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
AV
DD
Clean voltage input for the PLL.
I
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 2
Signal Functional Description
(Part 6 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
PPC405GP-3FE133CZ Power PC 405GP Embedded Processor
PPC405GP-3FE200C Power PC 405GP Embedded Processor
PPC405GP-3FE200CZ Power PC 405GP Embedded Processor
PPC405GP-3FE266C Power PC 405GP Embedded Processor
PPC405GP-3FE266CZ Power PC 405GP Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3FE133CZ 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3FE200C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray
PPC405GP-3FE200CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R
PPC405GP-3FE266C 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3FE266CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA T/R
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