參數(shù)資料
型號(hào)： PPC405GP-3EE266CZ
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GP Embedded Processor
中文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA413
封裝： 25 X 25 MM, PLASTIC, EBGA-413
文件頁(yè)數(shù)： 35/59頁(yè)
文件大?。?/td> 782K
代理商： PPC405GP-3EE266CZ
405GP – Power PC 405GP Embedded Processor
AMCC
35
Revision 2.03 – September 7, 2007
Data Sheet
Signal Functional Description
(Part 1 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD31:0
PCI Address/Data Bus. Multiplexed address and data bus.
I/O
5V tolerant
3.3V PCI
PCIC3:0[BE3:0]
PCI bus command and byte enables.
I/O
5V tolerant
3.3V PCI
PCIParity
PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3].
PCIParity is valid one cycle after either an address or data phase.
The PCI device that drove PCIAD0:31 is responsible for driving
PCIParity on the next PCI bus clock.
I/O
5V tolerant
3.3V PCI
PCIFrame
PCIFrame is driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
I/O
5V tolerant
3.3V PCI
2
PCIIRDY
PCIIRDY is driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer data.
I/O
5V tolerant
3.3V PCI
2
PCITRDY
The target of the current PCI transaction drives PCITRDY. Assertion
of PCITRDY indicates that the PCI target is ready to transfer data.
I/O
5V tolerant
3.3V PCI
2
PCIStop
The target of the current PCI transaction can assert PCIStop to
indicate to the requesting PCI master that it wants to end the current
transaction.
I/O
5V tolerant
3.3V PCI
2
PCIDevSel
PCIDevSel is driven by the target of the current PCI transaction. A
PCI target asserts PCIDevSel when it has decoded an address and
command encoding and claims the transaction.
I/O
5V tolerant
3.3V PCI
2
PCIIDSel
PCIIDSel is used during configuration cycles to select the PCI slave
interface for configuration.
I
5V tolerant
3.3V PCI
PCISErr
PCISErr is used for reporting address parity errors or catastrophic
failures detected by a PCI target.
I/O
5V tolerant
3.3V PCI
2
PCIPErr
PCIPErr is used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving PCIAD0:31,
PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in
which bad parity is detected.
I/O
5V tolerant
3.3V PCI
2
PCIClk
PCIClk is used as the asynchronous PCI clock when in
asynchronous mode. It is unused when the PCI interface is operated
synchronously with the PLB bus.
I
5V tolerant
3.3V PCI
PCIReset
PCI specific reset.
O
5V tolerant
3.3V PCI
PCIINT[PerWE]
PCI interrupt. Open-drain output (two states; 0 or open circuit)
or
Peripheral write enable. Low when any of the four PerWBE0:3 write
byte enables are low.
O
5V tolerant
3.3V PCI
PCIReq0[Gnt]
Multipurpose signal, used as PCIReq0 when internal arbiter is used,
and as Gnt when external arbiter is used.
I
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used.
I
5V tolerant
3.3V PCI
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3FE133C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays
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PPC405GP-3FE200C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray
PPC405GP-3FE200CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R
PPC405GP-3FE266C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
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