參數(shù)資料
型號： PPC405GP-3DE266C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GP Embedded Processor
中文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA456
封裝： 27 X 27 MM, PLASTIC, EBGA-456
文件頁數(shù)： 39/59頁
文件大?。?/td> 782K
代理商： PPC405GP-3DE266C
405GP – Power PC 405GP Embedded Processor
AMCC
39
Revision 2.03 – September 7, 2007
Data Sheet
External Master Peripheral Interface
PerClk
Peripheral clock to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
ExtReset
Peripheral reset to be used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
HoldReq
Hold Request, used by an external master to request ownership of
the peripheral bus.
I
5V tolerant
3.3V LVTTL
1, 5
HoldAck
Hold Acknowledge, used by the PPC405GP to transfer ownership of
peripheral bus to an external master.
O
5V tolerant
3.3V LVTTL
6
ExtReq
ExtReq is used by an external master to indicate it is prepared to
transfer data.
I
5V tolerant
3.3V LVTTL
1
ExtAck
ExtAck is used by the PPC405GP to indicate a data transfer cycle.
O
5V tolerant
3.3V LVTTL
6
HoldPri
Used by an external master to indicate the priority of a given external
master tenure.
I
5V tolerant
3.3V LVTTL
1
BusReq
Used when the PPC405GP needs to regain control of peripheral
interface from an external master.
O
5V tolerant
3.3V LVTTL
PerErr
An input used to indicate to the PPC405GP that an external slave
peripheral error occurred.
I
5V tolerant
3.3V LVTTL
1, 5
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternate clock to the internally
generated serial clock. Used in cases where the allowable internally
generated baud rates are not satisfactory. This input can be
individually connected to either UART.
I
5V tolerant
3.3V LVTTL
1
UART0_Rx
UART0 Serial Data In.
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Serial Data Out.
O
5V tolerant
3.3V LVTTL
6
UART0_DCD
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1
UART0_DSR
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1
UART0_CTS
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
UART0_DTR
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
6
UART0_RTS
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
6
UART0_RI
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL
1
UART1_Rx
UART1 Serial Data In.
I
5V tolerant
3.3V LVTTL
1
Signal Functional Description
(Part 5 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 34.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
PPC405GP-3DE266CZ Power PC 405GP Embedded Processor
PPC405GP-3EE200C Power PC 405GP Embedded Processor
PPC405GP-3EE200CZ Power PC 405GP Embedded Processor
PPC405GP-3EE266C Power PC 405GP Embedded Processor
PPC405GP-3EE266CZ Power PC 405GP Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3DE266CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA T/R
PPC405GP-3EE200C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3EE200CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3EE266C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 413-Pin EBGA Tray
PPC405GP-3EE266CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
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