參數(shù)資料
型號(hào): PPC405EP-3LB266C
廠商: APPLIEDMICRO INC
元件分類: 微控制器/微處理器
英文描述: PowerPC 405EP Embedded Processor
中文描述: 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA385
封裝: 31 X 31 MM, LEAD FREE, PLASTIC, EBGA-385
文件頁(yè)數(shù): 37/50頁(yè)
文件大小: 373K
代理商: PPC405EP-3LB266C
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
AMCC
37
c. T
CMax
= T
JMax
– P
×θ
JC
, where T
JMax
is maximum junction temperature and P is power consumption.
Table 9. Recommended DC Operating Conditions (Sheet 1 of 2)
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Notes:
1. PCI drivers meet PCI specifications.
2. See “5V-Tolerant Input Current” on page 38.
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Notes
Logic Supply Voltage (133, 200, 266MHz)
V
DD
+1.65
+1.8
+1.95
V
Logic Supply Voltage (333MHz)
V
DD
+1.7
+1.8
+1.9
V
I/O Supply Voltage
OV
DD
+3.0
+3.3
+3.6
V
PLL Supply Voltage (133, 200, 266MHz)
AV
DD
+1.65
+1.8
+1.95
V
PLL Supply Voltage (333MHz)
AV
DD
+1.7
+1.8
+1.9
V
Input Logic High
(1.8V CMOS receivers)
V
IH
0.65V
DD
V
DD
V
Input Logic High
(3.3V PCI receivers)
V
IH
0.5OV
DD
OV
DD
+0.5
V
Input Logic High
(3.3V LVTTL, 5V tolerant receivers)
V
IH
+2.0
+5.5
V
Input Logic Low
(1.8V CMOS receivers)
V
IL
0
0.65V
DD
V
Input Logic Low
(3.3V PCI receivers)
V
IL
-0.5
0.35OV
DD
V
Input Logic Low
(3.3V LVTTL, 5V tolerant receivers)
V
IL
0
+0.8
V
Output Logic High
(3.3V PCI receivers)
V
OH
0.9OV
DD
OV
DD
V
Output Logic High
(3.3V LVTTL, 5V tolerant receivers)
V
OH
+2.4
OV
DD
V
Output Logic Low
(3.3V PCI receivers)
V
OL
-0.5
0.35OV
DD
V
Output Logic Low
(3.3V LVTTL, 5V tolerant receivers)
V
OL
0
+0.4
V
Input Leakage Current
(no pull-up or pull-down)
I
IL1
0
0
μ
A
Input Leakage Current
(with internal pull-down)
I
IL2
0
200
μ
A
5V Tolerant I/O Input Current
I
IL4
±10
-325
μ
A
2
Input Max Allowable Overshoot
(1.8V CMOS receivers)
V
IMAO1.8
V
DD
+ 0.6
V
Input Max Allowable Overshoot
(3.3V LVTTL, 5V tolerant receivers)
V
IMAO
+5.5
V
Input Max Allowable Undershoot
(3.3V LVTTL, 5V tolerant receivers)
V
IMAU
-0.6
V
Output Max Allowable Overshoot
(3.3V LVTTL, 5V tolerant receivers)
V
OMAO
+5.5
V
Output Max Allowable Undershoot
(3.3V LVTTL, 5V tolerant receivers)
V
OMAU
-0.6
V
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