參數(shù)資料
型號: PNP-3350A-L22-G
廠商: RF MICRO DEVICES INC
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, QCC22
封裝: QFN-22
文件頁數(shù): 7/8頁
文件大小: 182K
代理商: PNP-3350A-L22-G
SPI Bus/MICROWIRE-Interface Timing Characteristics
Figure 6: MICROWIRE Interface Timing Diagram
DB31
DB30
DB1
DB0
DB2
~
CLOCK
DATA
CS
t1
t2
t3
t4
t6
t5
Parameter Limit at tmin to tmax Units
Test Conditions/Comments
t1
6
s min DATA to CLOCK setup time
t2
6
s min DATA to CLOCK hold time
t3
6
s min CLOCK high time
t4
6
s min CLOCK low time
t5
10
s min CLOCK to CS setup time
t6
10
s min CS pulse width (applies to MICROWIRE Interface only)
t7
6
s min CS to CLOCK setup time (applies to SPI BUS only)
Figure 7: SPI BUS Timing Diagram
DB31
DB30
DB1
DB0
DB2
~
CLOCK
DATA
CS
t1
t2
t3
t4
t5
t7
相關(guān)PDF資料
PDF描述
PNP-3350B-L22-G PHASE LOCKED LOOP, QCC22
PNP-3350-L22-G PHASE LOCKED LOOP, QCC22
PNP-3650C-L22-G PHASE LOCKED LOOP, QCC22
PNP-3650-L22-G PHASE LOCKED LOOP, QCC22
PNP-3650B-L22-G PHASE LOCKED LOOP, QCC22
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