參數(shù)資料
型號(hào): PMB2306R
廠商: INFINEON TECHNOLOGIES AG
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 120 MHz, PDSO16
封裝: PLASTIC, TSSOP-16
文件頁(yè)數(shù): 32/35頁(yè)
文件大?。?/td> 760K
代理商: PMB2306R
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Semiconductor Group
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66
9
DD
Positive supply voltage for serial control logic.
22
9
SS
Ground for serial control logic.
11
13
9
DD
1
Positive supply voltage for the preamplifiers, counters, phase
detector and charge pump.
911
9
SS
1
Ground for the preamplifiers, counters, phase detector and
charge pump.
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33
EN
/LQH%XV (QDEOH
Enable line of the serial control with internal pull-up resistor.
When EN = H the input signals CLK and DA are disabled
internally. When EN = L the serial control is activated. The
received data are transferred into the latches with the positive
edge of the EN-signal.
44
DA
/LQH%XV 'DWD
Serial data input with internal pull-up resistor. The last two bits
before the EN-signal define the destination address. In a byte-
oriented data structure the transmitted data have to end with
the EN-signal, i.e. bits to be filled in (don’t care) are transmitted
first.
55
CLK
/LQH%XV &ORFN
Clock line with internal pull-up resistor. The serial data are read
into the internal shift register with the positive edge (see pulse
diagram for serial data control).
77
MOD
0RGXOXV&RQWURO2XWSXW for external dual modulus prescaler.
The modulus output is low at the beginning of the cycle. When
the a-counter has reached its set value, MOD switches to high.
When the n-counter has reached its set value, MOD switches to
low again, and the cycle starts from the top. When the prescaler
has the counter factor P or P + 1 (P for MOD = H, P +1 for MOD
= L), the overall scaling factor is NP + A. The value of the a-
counter must be smaller than that of the n-counter. The trigger
edge of the modulus signal to the input signal can be selected
(see programming tables and MOD
A, B) according to the needs of the prescaler. In single modulus
operation and for standby operation in dual modulus operation,
the output is low.
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