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RELEASED
DATASHEET
PM73123 AAL1GATOR-8
ISSUE 2
PMC-2000097
8 LINK CES/DBCES AAL1 SAR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
Pin Name
ADAP_STBH
Type
Output AA19
Pin No.
Function
Adaptive Strobe indicates that the channel
status and byte difference are being played
out on the CGC_DOUT[3:0]. The nibbles are
identified by the values on CGC_LINE[4:0].
NCLK/
SRTS_DISB
Input
AA16
Network Clock is the ATM network-derived
clock used for SRTS. If this signal is tied
low, SRTS is disabled. Internally this clock
can be divided down to a lower frequency.
The resulting clock should be 2.43 MHz for
T1 and E1mode, 38.88 MHz for E3 mode
and 77.76 MHz for DS3 mode.
TL_CLK_OE
Input
Y16
Transmit Line Clock Output Enable controls
whether or not the TL_CLK lines are inputs
or outputs between the time of hardware
reset and when the CLK_SOURCE_TX bits
are read. If high, all TL_CLK pins are
outputs. If low, all TL_CLK pins are inputs.
There is an internal pull-down resistor, so all
TL_CLK pins are inputs if the pin is not
connected. The value of this input is
overwritten by the CLK_SOURCE_TX bits in
the LIN_STR_MODE memory register.
CGC_SER_D
Input
AA17
External Clock Generation Control Serial
Data is an input used to allow external clock
control circuitry to pass frequency
information into the internal clock
synthesizer.
CGC_VALID
Input
W18
External Clock Generation Control Valid
signal is an active high input indicating that
the data on CGC_SER_D is valid. This
signal must transition from a low to a high at
the first valid data on CGC_SER_D and must
stay high through the whole clock control
word.