參數(shù)資料
型號(hào): PM5364
廠商: PMC-Sierra, Inc.
英文描述: SONET/SDH Tributary Unit Payload Processor for 2488.32 Mbit/s
中文描述: 的SONET / SDH支路單元凈荷處理器/為2488.32兆?
文件頁(yè)數(shù): 1/2頁(yè)
文件大小: 57K
代理商: PM5364
PM5364
TUPP 2488
Released
SONET/SDH Tributary Unit Payload Processor for 2488.32 Mbit/s
PMC-2012695 (R6)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2004
FEATURES
Configurable, multi-channel, payload
processor for aligning SONET virtual
tributaries (VTs) or SDH tributary units
(TUs) in an STS-48/STM-16 or four
STS-12/STM-4 byte serial data streams.
Supports High Order (STS/AU) pointer
processing, payload processing, and
path termination/monitoring.
Supports Low Order (VT/TU) pointer
processing, payload processing and path
monitoring.
Integrates 4 x STS-12/STM-4 VT level
payload processors, 2 x ingress and
egress STS-1/STM-0 granular time slot
interchanges, 8 x ingress and egress
STS-12/STM-4 VT level time switches,
and an STS-192/STM-64 VT level space
switch (crossbar).
Integrated crossbar allows for
hair-pinning and OC-48 Add Drop Mux
(ADM) functionality.
Can be set up to operate in one of four
applications:
Hair-pinning (from line ingress to line
egress).
OC-48 ADM with internal crossbar.
NxOC-48 ADM with external crossbar
(internal crossbar is bypassed).
Payload Processing Only
Configuration.
On the line side, provides a 4 x 8-bit or
32-bit 77.76 MHz parallel TelecomBus
interface as well as redundant working
and protect ingress and egress serial
RASIO links. Links are configurable as:
4 x STS-12/STM-4 622.08 Mbit/s
SONET/SDH framed interfaces.
4 x STS-12/STM-4 777.6 Mbit/s
8B/10B encoded TelecomBus
interfaces.
1 x STS-48/STM-16 2.488 Gbit/s
SONET/SDH framed interface. This is
tied to one link and the other three
links are unused.
On the system side, provides redundant
working and protect ingress and egress
serial RASIO links. Links are configurable
as:
8 x STS-12/STM-4 622.08 Mbit/s
SONET/SDH framed interfaces.
8 x STS-12/STM-4 777.6 Mbit/s
8B/10B encoded TelecomBus
interfaces.
Independently configurable line and
system interface rates.
Provides optional PRBS generation and
monitoring features for CML off-line link
verification.
Supports Signal Fail (SF) and Signal
Degrade (SD) for each VT/TU path and
provides user-provisionable BER
thresholds for each SD/SF test that
range from 10
-3
to 10
-12
.
Supports contiguously concatenated
payloads (STS-3c, STS-12c/AU-4-4c,
STS-48c/AU-4-16c).
On the ingress path, provides optional
SDH payload conversion of:
AU3/VC3/C3 to an
AU4/VC4/TUG3/TU3/VC3/C3.
AU3/VC3/TUG2 to
AU4/VC4/TUG3/TUG2.
AU4/VC4/TUG3/TU3/VC3/C3 to
AU3/VC3/C3.
AU4/VC4/TUG3/TUG2 to
AU3/VC3/TUG2.
On the egress path, provides optional
SDH payload conversion of an
AU3/VC3/C3 to an
AU4/VC4/TUG3/TU3/VC3/C3.
Supports any legal mix of VT1.5, VT2,
VT3, VT6, TU11, TU12, TU2, or TU3
tributaries. Each VT group or TUG2 can
be configured to carry one of four
tributary types. TUG2s can be
multiplexed into VC3s or TUG3s. Each
TUG3 can also be configured to carry a
single TU3.
BLOCK DIAGRAM
Parallel Interface
(4 x 8-bit or 32-bit
TelecomBus)
High Order
Path
Processor
Serial
STS-1
Switch
Serial
Memory
(Time)
Switch
Memory
(Time)
Switch
Crossbar
(Space)
Switch
STS-1
Switch
High
Order
Path
Processor
Parallel Interface
(TelecomBus)
STS-1
Switch
Serial
Memory
(Time)
Switch
Memory
(Time)
Switch
Working
Protect
Working
Protect
Working
Protect
Low Order
Path
Processor
System Side
Serial Interfaces
4 x 777.6 Mbit/s or
4 x 622.08 Mbit/s
Line Side Serial Interfaces
(working and protect)
1 x 2488 Mbit/s or
4 x 777.6 Mbit/s or
4 x 622.08 Mbit/s
Working
Protect
STS-1
Switch
Serial
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