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參數(shù)資料
| 型號： | PLSI1032E-100LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 212K |
| 代理商： | PLSI1032E-100LJ |
10
Specifications
ispLSI and pLSI 1032E
UE0E0FR
NWEGS
Internal Timing Parameters
1
t
ob
t
sl
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0037B/1032E
Outputs
UNITS
-80
MIN.
-70
MIN.
MAX.
MAX.
DESCRIPTION
#
PARAM.
49 Output Buffer Delay
50 Output Buffer Delay, Slew Limited Adder
–
ns
ns
t
oen
t
odis
t
goe
51 I/O Cell OE to Output Enabled
52 I/O Cell OE to Output Disabled
53 Global OE
–
–
–
ns
ns
ns
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.5
ns
Global Reset
t
gr
Clocks
59 Global Reset to GLB and I/O Registers
ns
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
2.6
0.8
0.0
0.8
ns
ns
ns
ns
MIN. MAX.
2.1
10.0
5.7
5.7
4.3
1.5
4.5
3.1
1.8
0.0
1.8
–
–
–
–
–
1.5
–
1.5
0.8
0.0
0.8
2.6
10.0
6.2
6.2
5.8
1.5
4.6
1.5
1.8
0.0
1.8
-90
–
–
–
–
1.4
2.4
0.8
0.0
0.8
10.0
5.3
5.3
3.7
1.4
2.9
1.8
0.0
1.8
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