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參數(shù)資料
| 型號： | PLS159A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable Logic(可編程邏輯器件) |
| 中文描述： | 可編程邏輯（可編程邏輯器件） |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 198K |
| 代理商： | PLS159A |
00
01
11
2A
02
Figure 3.
:W
C*/D:X
A*B:Z
C:X
C*/D:X,Y
A*/B:Y
Philips Semiconductors Programmable Logic Devices
Application Note
AN15
PLS159A primer
October 1990
10
A D flip-flop may be implemented by first
entering an “A” in F/F MODE. Then enter “0”
in the row F
C
, which will unconditionally
enable the 3-State inverter between the J and
K inputs. The following logic equation may be
implemented as shown in Table 4, term 5
Q1: D=/A * /B * /C+E.
Notice that the entries in term 5, columns
Q(N)
0 to 7
are “A” and “.” instead of “H” and
“L” as in the case of J/K flip-flops. The entry
“A” will cause the fuse connecting to the “K”
input to be disconnected and the “J” fuse to
be intact. Whereas the entry “.” will cause
both fuses to be disconnected. This feature
enables the user to quickly recognize the
mode in which the flip-flops are operating
without having to go through the control
terms. Some commercially available device
programmers in the market may not have the
software capability to implement this feature,
in which case an “H” and a “–” may be used
in place of “A” and “.” respectively as shown
in Table 4, terms 8 and 9.
Of course, the term F
C
may have inputs
instead of zeros and dashes, in which case
the flip-flop modes are controlled dynamically.
When both the J and K inputs are “1’s”, the
flip-flop will toggle. A simple 3-bit counter
may be implemented using only AND terms
as shown in Table 4 terms 11, 12 and 13. The
logic equations for the three flip-flops are as
the following:
Q
5
:
unconditionally)
T=1;
(Q
5
toggles
Q
6
:
Q
5
=1)
T=Q
5
;
(Q
6
toggles when
Q
7
:
when Q
5
*
T=Q
5
* Q
6
;
(Q
7
toggles
Q
6
=1)
The above equations represent an octal
up-counter. However, since the outputs of the
flip-flops are inverted, the counting sequence
of the outputs is that of a down-counter.
The flip-flops may be asynchronously set and
reset by the Control AND terms PA/PB and
RA/RB respectively. As shown in Figure 1,
PA and RA controls flip-flops F
0
to F
3
, while
PB and RB control F
4
to F
7
.
In order to save the number of input pins, the
eight flip-flops may be synchronously loaded
directly from their own output pins. To use
this feature, EA and/or EB must be
programmed “A” or “–” so that the output
buffers may be disabled before loading. As
shown in Figure 1, every flip-flop has an
OR/NOR gate the input of which is directly
connected to the output pin and the outputs
of the OR/NOR are connected to the K and J
inputs respectively. This OR/NOR gate
inverts the input and feeds it to the flip-flop in
a “wire-OR” fashion. Therefore, when loading
data directly into the flip-flops from the output
pins, caution must be exercised to insure that
the inputs from the OR array does not
interfere with the data being loaded. For
example, if the data being loaded is a “1” on
the output pin, the J input will be a “0” and the
K input will be a “1”. If, at the same time, a “1”
is present at the J-input from the OR array,
the flip-flop will see “1’s” in both J and K
inputs. It will toggle as a result. The OR/NOR
gates are enabled by the Control AND terms
LA and LB. LA controls flip-flops F
0
to F
3
and
LB controls F
4
to F
7
.
All Control AND terms function and are
programmed in the same manner as the
other AND terms. The only difference is that
the Control AND terms are not connected to
the OR array.
The outputs of the flip-flops may be fed back
into the AND array as the present state,
Q(P). The output of the AND array into the
OR array and the inputs to the flip-flops is the
next state, Q(N). As an example, Figure 3 is
a state machine implemented in a PLS159A
as shown in Table 5, terms 0 to 6.
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| PLS159AN-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
| PLS167/BLA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fuse-Programmable PLD |
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