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參數(shù)資料
| 型號： | PLRXPL-VE-SH4-23-N |
| 廠商： | JDS UNIPHASE CORP |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 840-860nm, 9000Mbps(Tx), 9000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| 封裝： | ROHS COMPLIANT PACKAGE |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PLRXPL-VE-SH4-23-N |
7
8.5 G SFP+ 850 NM LIMITING TRANSCEIVER,
8 GIGABIT FIBRE CHANNEL COMPLIANT
Pin Number
Symbol
Name
Description
Receiver
8
LOS
Loss of Signal Out (OC)
Sufcient optical signal for potential BER < 1x10-12 = Logic “0”
Insufcient signal for potential BER < 1x10-12 = Logic “1”
This pin is open collector compatible, and should be pulled up
to Host Vcc with a 10 kΩ resistor.
10, 11, 14
VeeR
Receiver Signal Ground
These pins should be connected to signal ground on the host board.
The VeeR and VeeT signals are connected together within the module
and are isolated from the module case.
12
RD-
Receiver Negative
Light on = Logic “0” Output
DATA Out (PECL)
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
13
RD+
Receiver Positive
Light on = Logic “1” Output
DATA Out (PECL)
Receiver DATA output is internally AC coupled and series
terminated with a 50 Ω resistor.
15
VccR
Receiver Power Supply
This pin should be connected to a ltered +3.3 V power supply
on the host board. See Application schematics on page 4 for
ltering suggestions.
7
RS0
RX Rate Select (LVTTL)
This pin has an internal 30 kΩ pull-down to ground. A signal
on this pin will not affect module performance.
Transmitter
3
TX_Disable
Transmitter Disable In (LVTTL)
Logic “1” Input (or no connection) = Laser off
Logic “0” Input = Laser on
This pin is internally pulled up to VccT with a 10 kΩ resistor.
1, 17, 20
VeeT
Transmitter Signal Ground
These pins should be connected to signal ground on the host board.
The VeeR and VeeT signals are connected together within the module
and are isolated from the module case.
2
TX_Fault
Transmitter Fault Out (OC)
Logic “1” Output = Laser Fault (Laser off before t_fault)
This pin is open collector compatible, and should be pulled up
to Host Vcc with a 10 kΩ resistor.
16
VccT
Transmitter Power Supply
This pin should be connected to a ltered +3.3 V power supply
on the host board. See Application schematics on page 4 for
ltering suggestions.
18
TD+
Transmitter Positive
Logic “1” Input = Light on
DATA In (PECL)
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
19
TD-
Transmitter Negative
Logic “0” Input = Light on
DATA In (PECL)
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 Ω resistor.
9
RS1
TX Rate Select (LVTTL)
This pin has an internal 30 kΩ pulldown to ground. A signal
on this pin will not affect module performance.
Module Denition
4
SDA
Two-wire Serial Data
Serial ID with SFF 8472 Diagnostics.
Module denition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
5
SCL
Two-wire Serial Clock
Serial ID with SFF 8472 Diagnostics.
Module denition pins should be pulled up to Host Vcc with
appropriate resistors for the speed and capacitive loading of the
bus. See SFF8431.
6
MOD_ABS
Module Absent
Pin should be pulled up to Host Vcc with 10 kΩ resistor.
MOD_ABS is asserted “high” when the SFP+ module is
physically absent from the host slot.
SFP+ Optical Transceiver Pin Descriptions
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