- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368048 > PLL500-17TC-R (Electronic Theatre Controls, Inc.) Low Phase Noise VCXO (17MHz to 36MHz) PDF資料下載
參數(shù)資料
| 型號： | PLL500-17TC-R |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Phase Noise VCXO (17MHz to 36MHz) |
| 中文描述： | 低相位噪聲壓控振蕩器（17MHz至36MHz基本） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 215K |
| 代理商： | PLL500-17TC-R |
PLL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 03/29/05 Page 2
DIE PAD LAYOUT
DIE SPECIFICATIONS
Name
Value
Size
39 x 32 mil
GND
80 micron x 80 micron
10 mil
Reverse side
Pad dimensions
Thickness
PIN ASSIGNMENT (8-pin SOIC package) AND PAD DESCRIPTION (8-pin SOIC pack-
age)
Die Pad Position
X (
μ
m)
94.183
94.157
94.183
94.193
715.472
715.307
Name
Pin#
Y (
μ
m)
768.599
605.029
331.756
140.379
203.866
455.726
Type
Description
XIN
VDD
VCON
GND
CLK
VDD
1
2
3
4
5
6
I
P
I
P
O
P
Crystal input pin.
VDD power supply pin. Only one VDD pin is necessary.
Frequency control voltage input pin.
Ground pin.
Output clock pin.
VDD power supply pin. Only one VDD pin is necessary.
Output Enable input pin. Disables the output when low. Internal
pull-up enables output by default if pin is not connected to low.
Crystal output pin. Ref Clock input.
OE
7
715.472
626.716
I
XOUT
8
476.906
888.881
I
* OE (Output Enable) pin is not available in SOT-26 package, the output will always be enabled by the build in pull-up resister.
PIN ASSIGNMNET AND DESCRIPTION (6-pin SOIC package)
Name
Pin#
Type
Description
XOUT
GND
CLK
VCON
VDD
XIN
1
2
3
4
5
6
I
P
O
I
P
I
Crystal Output pin. Ref. Clock input.
Ground pin.
Output clock pin.
Frequency control voltage input pin.
VDD power supply pin.
Crystal input pin.
5
Y
X
(0,0)
(812,986)
3
32 mil
8
6
2
3
4
7
DIE ID:
PLL500-17: C500A0404-04A
1
XIN
VDD
CLK
GND
VCON
XOUT
OE^
VDD
Note: ^ denotes internal pull up
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL500-17TCL-R | Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17 | Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17DC | Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17SC | Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17SCL | Low Phase Noise VCXO (17MHz to 36MHz) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL500-17TI | 制造商:PLL 制造商全稱:PLL 功能描述:Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17TIL | 制造商:PLL 制造商全稱:PLL 功能描述:Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17TILR | 制造商:PLL 制造商全稱:PLL 功能描述:Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-17TIR | 制造商:PLL 制造商全稱:PLL 功能描述:Low Phase Noise VCXO (17MHz to 36MHz) |
| PLL500-27 | 制造商:PLL 制造商全稱:PLL 功能描述:Low Power CMOS Output VCXO Family (27MHz to 200MHz) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。