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參數(shù)資料
| 型號(hào)： | PLL1705DBQRG4 |
| 英文描述： | 3.3-V DUAL PLL MULTICLOCK GENERATOR |
| 中文描述： | 3.3 - V雙鎖相環(huán)MULTICLOCK發(fā)生器 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 187K |
| 代理商： | PLL1705DBQRG4 |
PLL1705
PLL1706
SLES046A
–
AUGUST 2002
–
REVISED SEPTEMBER 2002
www.ti.com
13
Mode Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
CE6
CE5
CE4
CE3
CE2
CE1
RSV
SR
FS2
FS1
Table 6. Register Mapping
REGISTER
BIT NAME
CE6
DESCRIPTION
MCKO2 output enable/disable
CE5
MCKO1 output enable/disable
CE4
SCKO1 output enable/disable
CE3
SCKO3 output enable/disable
Mode control
CE2
SCKO2 output enable/disable
CE1
SCKO0 output enable/disable
RSV
Reserved, must be 0
SR
Sampling rate select
FS[2:1]
Sampling frequency select
FS[2:1]: Sampling Frequency Group Select
FS2
0
0
1
1
FS1
0
1
0
1
SAMPLING FREQUENCY
48 kHz
44.1 kHz
32 kHz
Reserved
DEFAULT
O
SR: Sampling Rate Select
SR
0
1
SAMPLING RATE
Standard
Double
DEFAULT
O
CE [6:1]: Clock Output Control
CE1
–
CE6
0
1
CLOCK OUTPUT CONTROL
Clock output disable
Clock output enable
DEFAULT
O
While all the bits of CE [6:1] are 0, the PLL1706 goes into the power-down mode, all dynamic operation including PLLs
and the oscillator halt, but serial mode control is enabled for resumption.
CONNECTION DIAGRAM
Figure 14 shows the typical connection circuit for the PLL1705. There are four grounds for digital and analog power
supplies. However, the use of one common ground connection is recommended to avoid latch-up or other
power-supply-related troubles. Power supplies should be bypassed as close as possible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1705/6 are MPEG-2 based systems such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top boxes. The PLL1705/6 provides audio system clocks for a CD-DA DSP,
DVD DSP, Karaoke DSP, and DAC(s) from a 27-MHz video clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL1706DBQG4 | 3.3-V DUAL PLL MULTICLOCK GENERATOR |
| PLL1706DBQRG4 | 3.3-V DUAL PLL MULTICLOCK GENERATOR |
| PLL1720A | PHASE LOCKED LOOP |
| PLL200500 | Analog IC |
| PLL200500A | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1706 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3 V Dual PLL Multi-Clock Generator |
| PLL1706DBQ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQRG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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