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參數(shù)資料
| 型號(hào)： | PKF4910APINS |
| 廠商： | ERICSSON POWER MODULES AB |
| 元件分類： | 電源模塊 |
| 英文描述： | 1-OUTPUT 9.9 W DC-DC REG PWR SUPPLY MODULE |
| 封裝： | 8 MM HEIGHT, POWER, MODULE-18 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 269K |
| 代理商： | PKF4910APINS |
7
EN/LZT 146 86 R1A Ericsson Microelectronics AB, December 2001
The following typical resistor values can be used to adjust the
output voltage to 1.8 V or 2.5 V.
Output Voltage Adjust (Vadj)
Output voltage, VO, can be adjusted by using an external resistor
or other external circuitry. If other circuitry is used, the slew rate
has to be limited to maximum 5 V/ms. If pins 8 and 9 are not
connected together the output will decrease to a low value. To
increase VO a resistor should be connected between pin 8/9 and
17, and to decrease VO a resistor should be connected between pin
8 and 9 (see fig. 4).
Current Limiting Protection (Ilim)
The output power is limited at loads above the output current
limiting threshold (Ilim), specified as a minimum value.
Input and Output Impedance
Both the source impedance of the power feeding and the load
impedance will interact with the impedance of the DC/DC power
module.
It is most important to have the ratio between L and C as low as
possible, i.e. a low characteristic impedance, both at the input and
output, as the power modules have a low energy storage
capability. Use an electrolytic capacitor across the input if the
Capacitive Load
The PKF series has no maximum limit for capacitive load on the
output. The power module may operate in current limiting mode
during start-up, affecting the ramp-up and the start-up time. For
optimum start performance we recommend maximum 100
mF/A of
IO. Connect capacitors at the point of load for best performance.
Synchronization (Sync)
It is possible to synchronize the switching frequency to an
external symmetrical clock signal. The input can be driven by an
TTL-compatible output and referenced to the input pin 17.
Parallel Operation
Paralleling of several converters is easily accomplished by direct
connection of the output voltage terminal pins. The load regula-
tion characteristic is specifically designed for optimum paralleling
performance. Load sharing between converters will be within
±10%. It is recommended not to exceed PO = n × 0.9 × POmax,
where POmax is the maximum converter output power and n the
number of paralleled converters, to prevent overloading any of the
converters and thereby decreasing the reliability performance.
Characteristics
min
typ
max
unit
High level
2.2
6.5
V
Threshold level*)
1.2
1.7
2.2
V
Low level
0
0.4
V
Sink current
1.5
mA
Sync. frequency
520
688
kHz
*)
Rise time <10ns
Information given in this data sheet is believed to be accurate and reliable.
No responsibility is assumed for the consequences of its use nor for any infringement
of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of
Ericsson Microelectronics. These products are sold only according to
Ericsson Microelectronics’ general conditions of sale, unless otherwise confirmed in
writing. Specifications subject to change without notice.
Typical required resistor value to increase VO is given by:
Radj = 4.20 × (4.13 – VO)/(VO – VOi) k
W
where
VO is the desired output voltage,
VOi is the typical output voltage initial setting
Typical required resistor value to decrease VO is given by:
Radj = 17.6 × (VOi – VO)/(VO – 1.75) k
W
Output voltage
tolerance band
Rodnom (
W)
Standard values E24 (
W)
2.5 V ± 4%
19.4 k
33 k//47 k 1% 200 ppm
1.8 V ± 4%
500 k
1M//1M
1% 200 ppm
Figure 3
Ordering Information
Surface mount
PKF 4910A SI
Through hole
PKF 4910A PI *
Version
Part No.
* Optional PINS version without synchronization input.
source inductance is higher than 10
mH. Their equivalent series
resistance together with the capacitance acts as a lossless damping
filter. Suitable capacitor values are in the range 10–100
mF.
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