fdco DCO output f" />
參數(shù)資料
型號: PK60X256VMD100
廠商: Freescale Semiconductor
文件頁數(shù): 22/79頁
文件大?。?/td> 0K
描述: IC ARM CORTEX MCU 256K 144-MAP
產(chǎn)品培訓模塊: Kinetis® Cortex-M4 Microcontroller Family
標準包裝: 1
系列: Kinetis
核心處理器: ARM? Cortex?-M4
芯體尺寸: 32-位
速度: 100MHz
連通性: CAN,EBI/EMI,以太網(wǎng),I²C,IrDA,SDHC,SPI,UART/USART,USB,USB OTG
外圍設備: DMA,I²S,LVD,POR,PWM,WDT
輸入/輸出數(shù): 100
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.71 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 33x16b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 144-LBGA
包裝: 托盤
Table 15. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
20.97
25
MHz
2, 3
Mid range (DRS=01)
1280 × ffll_ref
40
41.94
50
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
83.89
100
MHz
fdco_t_DMX32 DCO output
frequency
Low range (DRS=00)
732 × ffll_ref
23.99
MHz
4, 5
Mid range (DRS=01)
1464 × ffll_ref
47.97
MHz
Mid-high range (DRS=10)
2197 × ffll_ref
71.99
MHz
High range (DRS=11)
2929 × ffll_ref
95.98
MHz
Jcyc_fll
FLL period jitter
fVCO = 48 MHz
fVCO = 98 MHz
180
150
ps
tfll_acquire FLL target frequency acquisition time
1
ms
PLL
fvco
VCO operating frequency
48.0
100
MHz
Ipll
PLL operating current
PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 48)
1060
A
Ipll
PLL operating current
PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
2 MHz, VDIV multiplier = 24)
600
A
fpll_ref
PLL reference frequency range
2.0
4.0
MHz
Jcyc_pll
PLL period jitter (RMS)
fvco = 48 MHz
fvco = 100 MHz
120
50
ps
Jacc_pll
PLL accumulated jitter over 1s (RMS)
fvco = 48 MHz
fvco = 100 MHz
1350
600
ps
Dlock
Lock entry frequency tolerance
± 1.49
± 2.98
%
Dunl
Lock exit frequency tolerance
± 4.47
± 5.97
%
tpll_lock
Lock detector detection time
150 × 10-6
+ 1075(1/
fpll_ref)
s
Peripheral operating requirements and behaviors
K60 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc.
29
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