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參數(shù)資料
| 型號： | PJ3842BCS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ELECTRONIC VACUUM, 120V RoHS Compliant: Yes |
| 中文描述： | 高性能電流模式控制器 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大小： | 375K |
| 代理商： | PJ3842BCS |
PJ3842B
High Performance Current Mode Controller
14-15
2002/01.ver.A
OPERATING DESCRIPTION
The PJ3842B series are high performance, fixed frequency, current mode controllers, They are specifically designed for Off-Line
and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A
representative block diagram is shown in Figure 17.
OSCILLATOR
The oscillator frequency is programmed by the values selected for the timing components R
T
and C
T
. Capacitor C
T
is charged
from the 5.0V reference through resistor R
T
to approximately 2.8V and discharge to 1.2V by an internal current sink.During the
discharge of C
T
, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes
the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows R
T
versus Oscillator
Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of C
T
. Note that many values of R
T
and C
T
will give the same oscillator frequency but only onne combination will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at T
J
=25
℃
. These internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. The
results are shown in Figure 3 and 4.
In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be
accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator
frequency should be set about 10% less than the clock frequency . A method for multi unit synchronization is shown in Figure 21.
By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved.
ER R OR AMPL IF IER
A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage
gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is
internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the
inverting input. The maximum input bias current is -2.0
μ
A which can cause an output voltage error that is equal to the product of
the input bias current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output voltage is offset by two diode
drops (
≈
1.4V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that
no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (V
OL
). This occurs when the power supply is
operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum
feedback resistance is limited by the amplifier's source current (0.5mA) and the required output voltage (V
OH
) to reach the
comparator’s 1.0V clamp level:
R
f(MIN)
= [3.0 (1.0V)+1.4V] / 0.5mA = 8800
CURRENT SENSE COMPARATOR AND PWM LATCH
The PJ3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated
when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus
the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch
configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is
converted to a voltageby inserting the ground referenced sense resistor R
S
in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak
inductor current under normal operating conditions is controlled by the voltage at pin 1 where:
I
PK
= [V(Pin 1) - 1.4V] / 3R
S
Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost, Under these
conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch
current is:
I
PK (MAX)
= 1.0V / R
S
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the
power dissipation of R
S
to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external
diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to
noise pickup can result if there is an excessive reduction of the I
PK
(max) clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit
an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output
rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike
duration will usually eliminate the instability: refer to Figure 26.
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