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參數(shù)資料
| 型號： | PJ3842 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Current Mode Controller |
| 中文描述： | 高性能電流模式控制器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 375K |
| 代理商： | PJ3842 |
PJ3842B
High Performance Current Mode Controller
8-15
2002/01.ver.A
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFET’s. It is capable of up to ±1.0A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active.This characteristic eliminates the need for an
external pull-down resistor.
The SOP-8 surface mount package provides separate pins
for
Vc(output
supply)
and
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level.The separate Vc supply input allows the designer
added fiexlbility in tailoring the drive voltage independent of
Vcc.A zener clamp is typically connected to this input when
driving power MOSFETs in systems where Vcc is greater
than 20V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET application.
Reference
The 5.0V bandgap reference is trimmed to±2.0% on the
PJ3842B.Its promary purpose to supply charging current to
the oscillator timing capacitor.The reference has short circuit
protection and is capable of providing in excess of 20mA for
powering additional control system circuitry.
Design Considerations
Do not attempt to construct the converter on wirewrap or
plug-in prototype boards.
High frequency circuit layout
techniques are imperative to prevent pulsewidth jitter.This is
usually caused by excessive noise pick-up imposed on the
Current Sense or Voltage Feedback inputs.Noise immunity
can be improved by lowering circuit impedances at these
points.The printed circuit layout should contain a ground
plane with lowcurrent signal and high-current switch and
output grounds returning separate paths back to the input
filter capacitor.Ceramic bypass capacitors(0.1
μ
F) connected
directly to Vcc,Vc, and Vref may be required depending upon
circuit layout . This provides a low impedance path for
filtering the high frequency noised. All high current loops
should be kept as short as possible using heavy copper runs to
minimize radiated EMI. The Error Amp compensation
circuitry and the converter output voltage divider should be
located close to the IC and as far as possible from the power
switch and other noise generating components.
Power
Ground.Proper
FIGURE 19-CONTINUOUS CURRENT WAVEFROMS
Current
mode
converters
oscillations when operating at a duty cycle greater than 50%
with
continuous
inductor
independent of the regulators closed loop characteristics and
is caused by the simultaneous operating conditions of fixed
frequency and peak current detecting. Figure 19A shows the
phenomenon graphically, At t
0
, switch conduction begins ,
causing the inductor current to rise at a slope of m
1
. This
slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m
2
,
until the next oscillator cycle. This unstable condition can be
shown if a perturbation is added to the control voltage ,
resulting in a small
Δ
l (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn-on(t
2
) is increased by
Δ
l+
Δ
l m
2
/m
1
.
The minimum current at the next cycle (t
3
) decreases to (
Δ
l+
Δ
l m
2
/m
1
)(m
2
/m
1
). This perturbation is multiplied by
m
2
/m
1
on each succeeding cycle , alternately increasing and
decreasing the inductor current at switch turn-on, Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If m
2
/m
1
is greater than 1, the converter will be unstable . Figure 19B
shows that by adding an artificial ramp that is synchronized
with the PWM clock to the control voltage . the
Δ
l
perturbation will decrease to zero on succeeding cycles. This
compensating ramp (m
3
) must have a slope equal to or
slightly greater than m
2
/2 for stability . With m
2
/2 slope
compensation , the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense inputs
(Figure 32).
can
exhibit
subharmonic
current,This
instability
is
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PDF描述 |
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| PJ3842B | High Performance Current Mode Controller |
| PJ3842BCD | High Performance Current Mode Controller |
| PJ3842BCS | ELECTRONIC VACUUM, 120V RoHS Compliant: Yes |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PJ3842B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Current Mode Controller |
| PJ3842BCD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Current Mode Controller |
| PJ3842BCS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Current Mode Controller |
| PJ3843 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Current Mode Controller |
| PJ3843B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Performance Current Mode Controller |
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