參數(shù)資料
型號: PIP3107-D
英文描述: TRANSISTOR | MOSFET | N-CHANNEL | 50V V(BR)DSS | TO-252AA
中文描述: 晶體管| MOSFET的| N溝道| 50V五(巴西)直資|到252AA
文件頁數(shù): 3/11頁
文件大?。?/td> 59K
代理商: PIP3107-D
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3103-T
OUTPUT CHARACTERISTICS
Limits are for -40C
T
mb
150C; typicals are for T
mb
= 25 C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Off-state
V
IS
= 0 V
I
D
= 10 mA
I
D
= 200 mA; t
p
300
μ
s;
δ
0.01
V
DS
= 40 V
V
(CL)DSS
Drain-source clamping voltage
50
-
-
V
50
60
70
V
I
DSS
Drain source leakage current
-
-
-
100
10
μ
A
μ
A
T
mb
= 25 C
0.1
On-state
V
IS
4 V; t
p
300
μ
s;
δ
0.01
I
D
= 100 mA
R
DS(ON)
Drain-source resistance
-
-
-
380
200
m
m
T
mb
= 25 C
150
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40C
T
mb
150C; typicals are for T
mb
= 25C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
Input threshold voltage
V
DS
= 5 V; I
D
= 1 mA
0.6
1.1
-
2.4
2.1
V
V
T
mb
= 25C
V
IS
= 5 V
V
IS
= 4 V
V
IS
= 5 V
V
IS
= 3 V
1.6
I
IS
Input supply current
normal operation;
100
80
220
195
400
330
μ
A
μ
A
μ
A
μ
A
I
ISL
Input supply current
protection latched;
200
130
400
250
650
430
V
ISR
t
lr
V
(CL)IS
R
IG
Protection reset voltage
1
reset time t
r
100
μ
s
V
IS1
= 5 V, V
IS2
< 1 V
I
I
= 1.5 mA
1.5
2
2.9
V
Latch reset time
10
40
100
μ
s
Input clamping voltage
5.5
-
8.5
V
Input series resistance
2
to gate of power MOSFET
T
mb
= 25C
-
33
-
k
1
The input voltage below which the overload protection circuits will be reset.
2
Not directly measureable from device terminals.
June 2001
3
Rev 1.000
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