參數(shù)資料
型號(hào): PIP3104-P
廠商: NXP SEMICONDUCTORS
元件分類: 外設(shè)及接口
英文描述: PowerMOS transistor Logic level TOPFET
中文描述: BUF OR INV BASED PRPHL DRVR, PSFM3
封裝: PLASTIC, TO-220AB, SOT-78B, SEP-3
文件頁(yè)數(shù): 4/6頁(yè)
文件大?。?/td> 32K
代理商: PIP3104-P
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level TOPFET
PIP3104-P
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40
C
T
mb
150
C; typicals are for T
mb
= 25
C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IS(TO)
Input threshold voltage
V
DS
= 5 V; I
D
= 1 mA
0.6
1.1
-
2.4
2.1
V
V
T
mb
= 25
C
V
IS
= 5 V
V
IS
= 4 V
V
IS
= 5 V
V
IS
= 3 V
1.6
I
IS
Input supply current
normal operation;
100
80
220
195
400
330
μ
A
μ
A
μ
A
μ
A
I
ISL
Input supply current
protection latched;
200
130
400
250
650
430
V
ISR
t
lr
V
(CL)IS
R
IG
Protection reset voltage
1
reset time t
r
100
μ
s
V
IS1
= 5 V, V
IS2
< 1 V
I
I
= 1.5 mA
1.5
2
2.9
V
Latch reset time
10
40
100
μ
s
Input clamping voltage
5.5
-
8.5
V
Input series resistance
2
to gate of power MOSFET
T
mb
= 25
C
-
33
-
k
SWITCHING CHARACTERISTICS
T
mb
= 25
C; V
DD
= 13 V; resistive load R
L
= 4
. Refer to waveform figure and test circuit.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
t
d on
t
r
t
d off
t
f
Turn-on delay time
V
IS
= 5 V
-
10
20
μ
s
μ
s
μ
s
μ
s
Rise time
-
20
40
Turn-off delay time
V
IS
= 0 V
-
30
60
Fall time
-
20
40
1
The input voltage below which the overload protection circuits will be reset.
2
Not directly measureable from device terminals.
May 2001
4
Rev 1.000
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