
Contents
Blue Chip Technology Ltd.
01271015.doc
1.0 INTRODUCTION.......................................................................... 1
ELECTROMAGNETIC COMPATIBILITY (EMC)................................. 2
EMC Specification ......................................................................... 3
2.0 USER ADJUSTMENTS ................................................................ 4
2.1 Selecting the Base Address (JP1) ............................................ 4
2.2 Setting the Interrupt Channel (JP2) .......................................... 6
3.0 PORT MAP .................................................................................. 7
3.1 Control Port Bit Functions ........................................................ 8
4.0 ELECTRICAL OPTIONS .............................................................. 9
4.1 Input Conditioning .................................................................... 9
4.2 Input/Output Connections......................................................... 9
4.3 Connector Pin Details............................................................. 11
5.0 OPERATING GUIDE.................................................................. 12
5.1 Using the Device .................................................................... 12
5.2 Programming Guide ............................................................... 13
Simple Inputs ............................................................................... 13
Simple Outputs ............................................................................ 13
Typical Register Setups ............................................................... 15
6.0 EXAMPLE PROGRAMS............................................................. 16
Example Program 1 ..................................................................... 16
Example Program 2 ..................................................................... 17
7.0 COMMERCIAL DATA ACQUISITION PACKAGES .................... 20
7.1 Use of the PIO-96 Board with ASYST .................................... 20
APPENDIX....................................................................................... 21
A1 I/O Address Map for PC/XT/AT Computers ............................ 21
A2 Hardware Interrupt Levels for PC/XT ...................................... 22
A3 Hardware Interrupt Levels for PC/AT ...................................... 23
DMA Channels............................................................................. 23