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參數(shù)資料
| 型號： | PIC32MX795F512L-80I/BG |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 52/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 512KB FLASH 121XBGA |
| 特色產(chǎn)品： | 32-Bit PIC? Microcontroller PIC32 32-Bit MCU Families |
| 標準包裝： | 184 |
| 系列： | PIC® 32MX |
| 核心處理器： | MIPS32? M4K? |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，以太網(wǎng)，I²C，SPI，UART/USART，USB OTG |
| 外圍設備： | 欠壓檢測/復位，DMA，POR，PWM，WDT |
| 程序存儲器容量： | 512KB（512K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 128K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 121-TFBGA |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 650 (CN2011-ZH PDF) |
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PIC32MX
DS61145K-page 56
2007-2012 Microchip Technology Inc.
19.2.4
ETAP_EJTAGBOOT
COMMAND
The
ETAP_EJTAGBOOT
command
causes
the
processor to fetch code from the debug exception
vector after a reset. This allows the programmer to
send instructions to the processor to execute, instead
of the processor fetching them from the normal reset
vector. The Reset value of the EjtagBrk, ProbTrap, and
ProbE
bits
follows
the
setting
of
the
internal
EJTAGBOOT indication.
If the EJTAGBOOT instruction has been given, and the
internal EJTAGBOOT indication is active, then the
Reset value of the three bits is set (‘1’), otherwise the
Reset value is clear (‘0’).
The results of setting these bits are:
Setting the EjtagBrk causes a Debug interrupt
exception to be requested right after the
processor Reset from the EJTAGBOOT instruction
The debug handler is executed from the EJTAG
memory because ProbTrap is set to indicate
debug vector in EJTAG memory at 0x FF20 0200
Service of the processor access is indicated
because ProbEn is set
With this configuration in place, an interrupt exception
will occur and the processor will fetch the handler from
the DMSEG at 0xFF200200. Since ProbEn is set, the
processor will wait for the instruction to be provided by
the probe.
19.2.5
ETAP_FASTDATA
COMMAND
The
ETAP_FASTDATA
command
provides
a
mechanism for quickly transferring data between the
processor and the probe.The width of the Fastdata
register is 1 bit. During a fast data access, the Fastdata
register is written and read (i.e., a bit is shifted in and a
bit is shifted out). During a fast data access, the Fast-
data register value shifted in specifies whether the fast
data access should be completed or not. The value
shifted out is a flag that indicates whether the fast data
access was successful or not (if completion was
requested). The FASTDATA access is used for efficient
block transfers between the DMSEG segment (on the
probe) and target memory (on the processor). An
“upload” is defined as a sequence that the processor
loads from target memory and stores to the DMSEG
segment. A “download” is a sequence of processor
loads from the DMSEG segment and stores to target
memory. The “Fastdata area” specifies the legal range
of DMSEG segment addresses (0xFF20.0000 to
0xFF20.000F) that can be used for uploads and down-
loads. The Data and Fastdata registers (selected with
the FASTDATA instruction) allow efficient completion of
pending Fastdata area accesses.
During Fastdata uploads and downloads, the proces-
sor will stall on accesses to the Fastdata area. The
PrAcc (processor access pending bit) will be 1 indicat-
ing the probe is required to complete the access. Both
upload and download accesses are attempted by shift-
ing in a zero SPrAcc value (to request access comple-
tion) and shifting out SPrAcc to see if the attempt will be
successful (i.e., there was an access pending and a
legal Fastdata area address was used).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As noted above, two conditions must be true for the
Fastdata access to succeed. These are:
PrAcc must be 1 (i.e., there must be a pending
processor access)
The Fastdata operation must use a valid Fastdata
area address in the DMSEG segment
(0xFF20.0000 to 0xFF20.000F)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| PIC32MX795F512L-80IPT | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:PIC32 Flash Programming Specification |
| PIC32MX795F512L-80V/BG | 功能描述:32位微控制器 - MCU 512KB 128KBR USB-OTG 2 CAN ETH 80MHz 10b RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PIC32MX795F512L-80V/PF | 功能描述:32位微控制器 - MCU 512KB 128KBR USB-OTG 2 CAN ETH 80MHz 10b RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PIC32MX795F512L-80V/PT | 功能描述:32位微控制器 - MCU 512KB 128KBR USB-OTG 2 CAN ETH 80MHz 10b RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PIC32MX795F512LT-80I/BG | 功能描述:32位微控制器 - MCU 512KB Flash 128KB USB ENET RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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