參數(shù)資料
型號： PIC32MX775F256L-80I/PF
廠商： Microchip Technology
文件頁數(shù)： 48/64頁
文件大小： 0K
描述： IC MCU 32BIT 256K FLASH 100TQFP
特色產(chǎn)品： 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標準包裝： 90
系列： PIC® 32MX
核心處理器： MIPS32? M4K?
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，以太網(wǎng)，I²C，SPI，UART/USART，USB OTG
外圍設備： 欠壓檢測/復位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 85
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 650 (CN2011-ZH PDF)
PIC32MX
DS61145K-page 52
2007-2012 Microchip Technology Inc.
19.0
TAP CONTROLLERS
TABLE 19-1:
MCHP TAP INSTRUCTIONS
19.1
Microchip TAP Controllers (MTAP)
19.1.1
MTAP_COMMAND
INSTRUCTION
MTAP_COMMAND
selects the MCHP Command Shift
register. See Table 19-2 for available commands.
19.1.1.1
MCHP_STATUS
INSTRUCTION
MCHP_STATUS
returns the 8-bit Status value of the
Microchip TAP controller. Table 19-3 shows the format
of the Status value returned.
19.1.1.2
MCHP_ASSERT_RST
INSTRUCTION
MCHP_ASSERT_RST
performs a persistent device
Reset. It is similar to asserting and holding MCLR with
the exception that test modes are not detected. Its
associated Status bit is DEVRST.
19.1.1.3
MCHP_DE_ASSERT_RST
INSTRUCTION
MCHP_DE_ASSERT_RST
removes
the
persistent
device Reset. It is similar to de-asserting MCLR. Its
associated Status bit is DEVRST.
19.1.1.4
MCHP_ERASE
INSTRUCTION
MCHP_ERASE
performs a Chip
Erase
. The CHIP_
ERASE
command sets an internal bit that requests the
Flash Controller to perform the erase. Once the control-
ler becomes busy, as indicated by FCBUSY (Status
bit), the internal bit is cleared.
19.1.1.5
MCHP_FLASH_ENABLE
INSTRUCTION
MCHP_FLASH_ENABLE
sets the FAEN bit, which con-
trols processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
19.1.1.6
MCHP_FLASH_DISABLE
INSTRUCTION
MCHP_FLASH_DISABLE
clears the FAEN bit which
controls processor accesses to the Flash memory. The
FAEN bit’s state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
19.1.2
MTAP_SW_MTAP
INSTRUCTION
MTAP_SW_MTAP
switches the TAP instruction set to the
MCHP TAP instruction set.
19.1.3
MTAP_SW_ETAP
INSTRUCTION
MTAP_SW_ETAP
effectively switches the TAP instruc-
tion set to the EJTAG TAP instruction set. It does this
by holding the EJTAG TAP controller in the Run Test/
Idle state until a MTAP_SW_ETAP instruction is decoded
by the MCHP TAP controller.
19.1.4
MTAP_IDCODE
INSTRUCTION
MTAP_IDCODE
returns the value stored in the DEVID
register.
TABLE 19-2:
MTAP_COMMAND DR
COMMANDS
Command
Value
Description
MTAP_COMMAND
5’h0x07
TDI and TDO connected to MCHP Command Shift register (See Table 19-2).
MTAP_SW_MTAP
5’h0x04
Switch TAP controller to MCHP TAP controller.
MTAP_SW_ETAP
5’h0x05
Switch TAP controller to EJTAG TAP controller.
MTAP_IDCODE
5’h0x01
Select Chip Identification Data register.
Command
Value
Description
MCHP_STATUS
8’h0x00
NOP
and return Status.
MCHP_ASSERT_RST
8’h0xD1
Requests the reset controller to assert device Reset.
MCHP_DE_ASSERT_RST
8’h0xD0
Removes the request for device Reset, which causes the reset
controller to de-assert device Reset if there is no other source
requesting Reset (i.e., MCLR).
MCHP_ERASE
8’h0xFC
Cause the Flash controller to perform a Chip Erase.
MCHP_FLASH_ENABLE
8’h0xFE
Enables fetches and loads to the Flash (from the processor).
MCHP_FLASH_DISABLE
8’h0xFD
Disables fetches and loads to the Flash (from the processor).
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