參數(shù)資料
型號: PIC32MX775F256L-80I/BG
廠商: Microchip Technology
文件頁數(shù): 64/64頁
文件大小: 0K
描述: IC MCU 32BIT 256KB FLASH 121XBGA
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標(biāo)準(zhǔn)包裝: 184
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: CAN,以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 121-TFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 650 (CN2011-ZH PDF)
2007-2012 Microchip Technology Inc.
DS61145K-page 9
PIC32MX
5.1
Programming Interface
Figure 5-2 shows the basic programming interface in
PIC32MX devices. Descriptions of each interface block
are provided in subsequent sections.
FIGURE 5-2:
BASIC PIC32MX PROGRAMMING INTERFACE BLOCK DIAGRAM
5.1.1
ETAP
This block serially feeds instructions and data into the
CPU.
5.1.2
MTAP
In addition to the EJTAG TAP (ETAP) controller, the
PIC32MX device uses a second proprietary TAP con-
troller for additional operations. The Microchip TAP
(MTAP) controller supports two instructions relevant to
programming:
MTAP_COMMAND
and
TAP
switch
Instructions. See Table 19-1 for a complete list of
Instructions. The MTAP_COMMAND instruction provides
a mechanism for a JTAG probe to send commands to
the device through its Data register.
The programmer sends commands by shifting in the
MTAP_COMMAND
instruction through the SendCommand
pseudo operation, and then sending MTAP_COMMAND
DR
commands through XferData pseudo operation
(see Table 19-2 for specific commands).
The probe does not need to issue a MTAP_COMMAND
instruction for every command shifted into the Data
register.
5.1.3
2-WIRE TO 4-WIRE
This block converts the 2-wire ICSP interface to the
4-wire JTAG interface.
5.1.4
CPU
The CPU executes instructions at 8 MHz through the
internal oscillator.
5.1.5
FLASH CONTROLLER
The Flash controller controls erasing and programming
of the Flash memory on the device.
5.1.6
FLASH MEMORY
The PIC32MX device Flash memory is divided into two
logical Flash partitions consisting of the Boot Flash
Memory (BFM) and Program Flash Memory (PFM).
The
Boot
Flash
Memory
map
extends
from
0x1FC00000 to 0x1FC02FFF, and the Program Flash
Memory
map
extends
from
0x1D000000
to
0x1D07FFFF.
Code storage begins with the BFM and supports up to
12 Kbytes. It continues with the PFM, which supports
up to 512 Kbytes. Table 5-1 shows the program mem-
ory size of each device variant. Each Flash partition is
divided into pages, which represent the smallest block
of memory that can be erased. Depending on the
device, page sizes are either 256 words (1024 bytes) or
1024 words (4096 bytes). Row size indicates the num-
ber of words that are programmed with the row pro-
gram command. There are always 8 rows within a
page; therefore, devices with 128 word page sizes
have 32 word (128 byte) row sizes and devices with
1024 word page sizes have 128 word (512 byte) row
sizes.
TMS
TCK
TDI
TDO
or
PGECx
PGEDx
ETAP
CPU
MTAP
2-wire
Flash
to
4-wire
Controller
Memory
Common
VDD
VSS
MCLR
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