參數(shù)資料
型號: PIC32MX675F512L-80I/PT
廠商: Microchip Technology
文件頁數(shù): 49/64頁
文件大小: 0K
描述: IC MCU 32BIT 512KB FLASH 100TQFP
特色產(chǎn)品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 32MX
核心處理器: MIPS32? M4K?
芯體尺寸: 32-位
速度: 80MHz
連通性: 以太網(wǎng),I²C,SPI,UART/USART,USB OTG
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 512KB(512K x 8)
程序存儲器類型: 閃存
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 650 (CN2011-ZH PDF)
配用: 876-1000-ND - PIC32 BREAKOUT BOARD
2007-2012 Microchip Technology Inc.
DS61145K-page 53
PIC32MX
TABLE 19-3:
MCHP STATUS VALUE
TABLE 19-4:
EJTAG TAP INSTRUCTIONS
Bit
Range
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7:0
CPS
0
NVMERR(1)
0
CFGRDY
FCBUSY
FAEN
DEVRST
bit 7
CPS: Code-Protect State bit
1
= Device is not code-protected
0
= Device is code-protected
bit 6
Unimplemented: Read as ‘0’
bit 5
NVMERR: NVMCON Status bit(1)
1
= An Error occurred during NVM operation
0
= An Error did not occur during NVM operation
bit 4
Unimplemented: Read as ‘0’
bit 3
CFGRDY: Code-Protect State bit
1
= Configuration has been read and CP is valid
0
= Configuration has not been read
bit 2
FCBUSY: Flash Controller Busy bit
1
= Flash controller is busy (Erase is in progress)
0
= Flash controller is not busy (either erase has not started or it has finished)
bit 1
FAEN: Flash Access Enable bit
This bit reflects the state of CFGCON.FAEN.
1
= Flash access is enabled
0
= Flash access is disabled (i.e., processor accesses are blocked)
bit 0
DEVRST: Device Reset State bit
1
= Device Reset is active
0
= Device Reset is not active
Note 1:
This bit is available in PIC32MX1X0 and PIC32MX2X0 devices only.
Command
Value
Description
ETAP_ADDRESS
5’h0x08
Select Address register.
ETAP_DATA
5’h0x09
Select Data register.
ETAP_CONTROL
5’h0x0A
Select EJTAG Control register.
ETAP_EJTAGBOOT
5’h0x0C
Set EjtagBrk, ProbEn and ProbTrap to ‘1’ as Reset value.
ETAP_FASTDATA
5’h0x0E
Selects the Data and Fastdata registers.
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