
PIC32MX5XX/6XX/7XX
DS61156G-p
age
116
2009-
2011
Microchip
T
echnolo
gy
Inc.
9260
EMAC1
SUPP
31:16
—
0000
15:0
—
RESET
RMII
—
SPEED
RMII
—
1000
9270
EMAC1
TEST
31:16
—
0000
15:0
—
TESTBP
TESTPAUSE SHRTQNTA
0000
9280
EMAC1
MCFG
31:16
—
0000
15:0
RESET
MGMT
—
CLKSEL<3:0>
NOPRE
SCANINC 0020
9290
EMAC1
MCMD
31:16
—
0000
15:0
—
—SCAN
READ
0000
92A0
EMAC1
MADR
31:16
—
0000
15:0
—
PHYADDR<4:0>
—
REGADDR<4:0>
0100
92B0
EMAC1
MWTD
31:16
—
0000
15:0
MWTD<15:0>
0000
92C0
EMAC1
MRDD
31:16
—
0000
15:0
MRDD<15:0>
0000
92D0
EMAC1
MIND
31:16
—
0000
15:0
—
LINKFAIL
NOTVALID
SCAN
MIIMBUSY 0000
9300
EMAC1
SA0(2)
31:16
—
xxxx
15:0
STNADDR6<7:0>
STNADDR5<7:0>
xxxx
9310
EMAC1
SA1(2)
31:16
—
xxxx
15:0
STNADDR4<7:0>
STNADDR3<7:0>
xxxx
9320
EMAC1
SA2(2)
31:16
—
xxxx
15:0
STNADDR2<7:0>
STNADDR1<7:0>
xxxx
TABLE 4-47:
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
V
irtual
Addr
es
s
(B
F
88_#)
R
egist
er
Name
Bit
Range
Bits
A
llRe
se
ts
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2:
Reset values default to the factory programmed value.