![](http://datasheet.mmic.net.cn/Microchip-Technology/PIC32MX250F128D-I-ML_datasheet_99580/PIC32MX250F128D-I-ML_69.png)
2011-20
12
Micro
chip
Te
chnology
Inc.
Prelimina
ry
D
S
6
1168D-p
age
69
PIC32MX1XX/2XX
TABLE 4-25:
RTCC REGISTER MAP(1)
V
irtual
A
ddress
(BF80_#
)
Regis
ter
Na
m
e
Bit
Range
Bits
All
R
eset
s
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
0200 RTCCON
31:16
—
CAL<9:0>
0000
15:0
ON
—SIDL
—
RTSECSEL RTCCLKON
—
RTCWREN RTCSYNC HALFSEC RTCOE 0000
0210 RTCALRM
31:16
—
0000
15:0 ALRMEN
CHIME
PIV
ALRMSYNC
AMASK<3:0>
ARPT<7:0>
0000
0220 RTCTIME
31:16
HR10<3:0>
HR01<3:0>
MIN10<3:0>
MIN01<3:0>
xxxx
15:0
SEC10<3:0>
SEC01<3:0>
—
xx00
0230 RTCDATE
31:16
YEAR10<3:0>
YEAR01<3:0>
MONTH10<3:0>
MONTH01<3:0>
xxxx
15:0
DAY10<3:0>
DAY01<3:0>
—
WDAY01<3:0>
xx00
0240 ALRMTIME
31:16
HR10<3:0>
HR01<3:0>
MIN10<3:0>
MIN01<3:0>
xxxx
15:0
SEC10<3:0>
SEC01<3:0>
—
xx00
0250 ALRMDATE
31:16
—
MONTH10<3:0>
MONTH01<3:0>
00xx
15:0
DAY10<3:0>
DAY01<3:0>
—
WDAY01<3:0>
xx0x
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
information.
TABLE 4-26:
CTMU REGISTER MAP(1)
V
irtual
Ad
dress
(BF80_
#)
Regi
ster
Nam
e
Bit
Range
Bits
Al
lReset
s
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
A200 CTMUCON
31:16 EDG1MOD EDG1POL
EDG1SEL<3:0>
EDG2STAT EDG1STAT EDG2MOD EDG2POL
EDG2SEL<3:0>
—
0000
15:0
ON
—
CTMUSIDL
TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
ITRIM<5:0>
IRNG<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
1:
information.