TDLY
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    參數(shù)資料
    型號: PIC24HJ64GP206A-E/MR
    廠商: Microchip Technology
    文件頁數(shù): 57/84頁
    文件大?。?/td> 0K
    描述: IC MCU 16BIT 64KB FLASH 64QFN
    標準包裝: 40
    系列: PIC® 24H
    核心處理器: PIC
    芯體尺寸: 16-位
    速度: 40 MIP
    連通性: I²C,IrDA,LIN,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
    輸入/輸出數(shù): 53
    程序存儲器容量: 64KB(22K x 24)
    程序存儲器類型: 閃存
    RAM 容量: 8K x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 18x10b/12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 125°C
    封裝/外殼: 64-VFQFN 裸露焊盤
    包裝: 管件
    dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
    DS70152H-page 60
    2010 Microchip Technology Inc.
    P9b
    TDLY5
    Delay between PGDx
    ↓ by Programming
    Executive to PGDx Released by
    Programming Executive
    15
    23
    μs—
    P10
    TDLY6
    PGCx Low Time After Programming
    400
    ns
    P11
    TDLY7
    Bulk Erase Time
    330
    ms
    See Note 2
    P12
    TDLY8
    Page Erase Time
    19.5
    ms
    See Note 2
    P13
    TDLY9
    Row Programming Time
    1.28
    ms
    See Note 2
    P14
    TR
    MCLR Rise Time to Enter ICSP mode
    1.0
    μs—
    P15
    TVALID
    Data Out Valid from PGCx
    10
    ns
    P16
    TDLY10 Delay between Last PGCx
    ↓and MCLR ↓
    0—
    s
    P17
    THLD3MCLR
    ↓ to VDD
    —100
    ns
    P18
    TKEY1
    Delay from First MCLR
    ↓ to First PGCx ↑
    for Key Sequence on PGDx
    1—
    μs—
    P19
    TKEY2
    Delay from Last PGCx
    ↓for Key Sequence
    on PGDx to Second MCLR
    25
    ns
    P20
    TDLY11 Maximum Wait Time for Configuration
    Register Programming
    —25
    ms
    P21
    TMCLRH MCLR High Time
    500
    μs—
    TABLE 8-1:
    AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED)
    Standard Operating Conditions
    Operating Temperature: –40C-85C. Programming at 25C is recommended.
    Param
    No.
    Symbol
    Characteristic
    Min
    Max
    Units
    Conditions
    Note 1: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within
    ±0.3V of VDD and VSS, respectively.
    2: Time depends on the FRC accuracy and the value of the FRC Oscillator tuning register. Refer to
    “Electrical Characteristics” section in the specific device data sheet.
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