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    參數(shù)資料
    型號(hào): PIC24HJ64GP202-I/SO
    廠商: Microchip Technology
    文件頁(yè)數(shù): 32/84頁(yè)
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 64K 28SOIC
    標(biāo)準(zhǔn)包裝: 27
    系列: PIC® 24H
    核心處理器: PIC
    芯體尺寸: 16-位
    速度: 40 MIP
    連通性: I²C,PMP,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
    輸入/輸出數(shù): 21
    程序存儲(chǔ)器容量: 64KB(22K x 24)
    程序存儲(chǔ)器類型: 閃存
    RAM 容量: 8K x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b/12b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
    包裝: 管件
    產(chǎn)品目錄頁(yè)面: 648 (CN2011-ZH PDF)
    配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
    dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
    DS70152H-page 38
    2010 Microchip Technology Inc.
    TABLE 5-4:
    SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY
    5.6
    Writing Code Memory
    The procedure for writing code memory is similar to the
    procedure for writing the Configuration registers,
    except that 64 instruction words are programmed at a
    time. To facilitate this operation, working registers,
    W0:W5, are used as temporary holding registers for the
    data to be programmed.
    Table 5-5 shows the ICSP programming details,
    including the serial pattern with the ICSP command
    code, which must be transmitted Least Significant bit
    first using the PGCx and PGDx pins (see Figure 5-2).
    In Step 1, the Reset vector is exited. In Step 2, the
    NVMCON register is initialized for programming of
    code memory. In Step 3, the 24-bit starting destination
    address for programming is loaded into the TBLPAG
    register and W7 register. The upper byte of the
    starting destination address is stored in TBLPAG and
    the lower 16 bits of the destination address are stored
    in W7.
    To minimize the programming time, the same packed
    instruction format that the programming executive uses
    is utilized (see Figure 4-4). In Step 4, four packed
    instruction words are stored in working registers,
    W0:W5, using the MOV instruction and the read pointer,
    W6, is initialized. The contents of W0:W5 holding the
    packed instruction word data are illustrated in
    Figure 5-7. In Step 5, eight TBLWT instructions are used
    to copy the data from W0:W5 to the write latches of
    code memory. Since code memory is programmed 64
    instruction words at a time, Steps 4 and 5 are repeated
    16 times to load all the write latches (Step 6).
    After the write latches are loaded, programming is
    initiated by writing to the NVMCON register in Steps 7
    and 8. In Step 9, the internal PC is reset to 0x200. This is
    a precautionary measure to prevent the PC from
    incrementing into unimplemented memory when large
    devices are being programmed. Lastly, in Step 10,
    Steps 3-9 are repeated until all of code memory is
    programmed.
    FIGURE 5-7:
    PACKED INSTRUCTION
    WORDS IN W0:W5
    Command
    (Binary)
    Data
    (Hex)
    Description
    Step 1: Exit the Reset vector.
    0000
    040200
    000000
    GOTO
    0x200
    GOTO
    0x200
    NOP
    Step 2: Set the NVMCON to erase all program memory.
    0000
    2404FA
    883B0A
    MOV
    #0x404F, W10
    MOV
    W10, NVMCON
    Step 3: Initiate the erase cycle.
    0000
    A8E761
    000000
    BSET
    NVMCON, #WR
    NOP
    Step 4: Wait for Bulk Erase operation to complete and make sure WR bit is clear.
    Externally time ‘P11’ msec (see Section 8.0 “AC/DC Characteristics and
    Timing Requirements”) to allow sufficient time for the Bulk Erase operation to
    complete.
    15
    8
    7
    0
    W0
    LSW0
    W1
    MSB1
    MSB0
    W2
    LSW1
    W3
    LSW2
    W4
    MSB3
    MSB2
    W5
    LSW3
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