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dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
DS70152H-page 70
2010 Microchip Technology Inc.
dsPIC33FJ128MC204
Disabled
CFGB + SUM(0:0157FF)
0x01CC
0xFFCE
Enabled
CFGB
0x05CA
dsPIC33FJ128MC506
Disabled
CFGB + SUM(0:0157FF)
0x01BC
0xFFBE
Enabled
CFGB
0x05BA
dsPIC33FJ128MC510
Disabled
CFGB + SUM(0:0157FF)
0x01BC
0xFFBE
Enabled
CFGB
0x05BA
dsPIC33FJ128MC706
Disabled
CFGB + SUM(0:0157FF)
0x01BC
0xFFBE
Enabled
CFGB
0x05BA
dsPIC33FJ128MC708
Disabled
CFGB + SUM(0:0157FF)
0x01BC
0xFFBE
Enabled
CFGB
0x05BA
dsPIC33FJ128MC710
Disabled
CFGB + SUM(0:0157FF)
0x01BC
0xFFBE
Enabled
CFGB
0x05BA
dsPIC33FJ256MC510
Disabled
CFGB + SUM(0:02ABFF)
0x03BC
0x01BE
Enabled
CFGB
0x05BA
dsPIC33FJ256MC710
Disabled
CFGB + SUM(0:02ABFF)
0x03BC
0x01BE
Enabled
CFGB
0x05BA
dsPIC33FJ128MC802
Disabled
CFGB + SUM(0:0157FF)
0x01CC
0xFFCE
Enabled
CFGB
0x05CA
dsPIC33FJ128MC804
Disabled
CFGB + SUM(0:0157FF)
0x01CC
0xFFCE
Enabled
CFGB
0x05CA
PIC24HJ12GP201
Disabled
CFGB + SUM(0:001FFF)
0xD43D
0xD23F
Enabled
CFGB
0x043B
TABLE D-1:
CHECKSUM COMPUTATION (CONTINUED)
Device
Read Code
Protection
Checksum Computation
Erased
Value
Value with
0xAAAAAA at 0x0
and Last
Code Address
Item Description:
SUM(a:b) = Byte sum of locations a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) +
(FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0x0F) + (FICD & 0xE3))
(for dsPIC33FJ06GS101/102/202 and dsPIC33FJ16GS402/404/502/504 devices)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) +
(FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xF7) + (FICD & 0xE3))
(for dsPIC33FJ12GP201/202, dsPIC33FJ12MC201/202, PIC24HJ12GP201/202, dsPIC33FJ32GP202/204,
dsPIC33FJ32MC202/204, PIC24HJ32GP202/204, dsPIC33FJ16GP304, dsPIC33FJ16MC304, PIC24HJ16GP304,
dsPIC33FJ32GP302/304, dsPIC33FJ32MC302/304 and PIC24HJ32GP302/304 devices)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) +
(FOSCSEL & 0x87) + (FOSC & 0xE7) + (FWDT & 0xDF) + (FPOR & 0xF7) + (FICD & 0xE3))
(for dsPIC33FJ64GP202/204, dsPIC33F64MC202/204, PIC24HJ64GP202/204, dsPIC33FJ64GP802/804,
dsPIC33FJ64MC802/804, PIC24HJ64GP502/504, dsPIC33FJ128GP202/204, dsPIC33FJ128MC202/204,
PIC24HJ128GP202/204, dsPIC33FJ128GP802/804, dsPIC33FJ128MC802/804 and PIC24HJ128GP502/504 devices)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) +
(FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for dsPIC33FJXXXGPX06/X08/X10, dsPIC33FJ64GPX06A/X08A/X10A, dsPIC33FJ128GPX06A/X08A/X10A,
dsPIC33FJXXXMCX06/X08/X10, dsPIC33FJ64MCX06A/X08A/X10A, dsPIC33FJ128MCX06A/X08A/X10A,
PIC24HJXXXGPX06/X08/X10, PIC24HJ64GPX06A/X08A/X10A and PIC24HJ128GPX06A/X08A/X10A devices)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0xCF) + (FSS & 0xCF) + (FGS & 0x07) +
(FOSCSEL & 0xA7) + (FOSC & 0xC7) + (FWDT & 0xFF) + (FPOR & 0xE7) + (FICD & 0xE3))
(for dsPIC33FJ256GP506A/510A/710A, dsPIC33FJ256MC510A/710A and PIC24HJ256GP206A/210A/610A devices)
CFGB = Configuration Block (masked) = Byte sum of ((FBS & 0x0F) + (FGS & 0x07) + (FOSCSEL & 0x87) +
(FOSC & 0xC7) + (FWDT & 0xDF) + (FPOR & 0x67) + (FICD & 0xE3))
(for dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 devices)