參數(shù)資料
型號(hào): PIC24FJ64GA006T-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 219/258頁(yè)
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 64TQFP
產(chǎn)品培訓(xùn)模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 64KB(22K x 24)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA160011-ND - DAUGHTER BOARD PICDEM LCD 16F91X
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164327-ND - MODULE SKT FOR 64TQFP
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2005-2012 Microchip Technology Inc.
DS39747F-page 63
PIC24FJ128GA010 FAMILY
7.0
INTERRUPT CONTROLLER
The PIC24F interrupt controller reduces the numerous
peripheral interrupt request signals to a single interrupt
request signal to the PIC24F CPU. It has the following
features:
Up to 8 processor exceptions and software traps
7 user-selectable priority levels
Interrupt Vector Table (IVT) with up to 118 vectors
A unique vector for each interrupt or exception
source
Fixed priority within a specified user priority level
Alternate Interrupt Vector Table (AIVT) for debug
support
Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 7-1.
The IVT resides in program memory, starting at location,
000004h. The IVT contains 126 vectors, consisting of
8 non-maskable trap vectors, plus up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt vec-
tor location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this is linked to their position in the vector table.
All other things being equal, lower addresses have a
higher natural priority. For example, the interrupt asso-
ciated with Vector 0 will take priority over interrupts at
any other vector address.
PIC24FJ128GA010 family devices implement non-
maskable traps and unique interrupts. These are
summarized in Table 7-1 and Table 7-2.
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24F device clears its registers in response to a
Reset which forces the PC to zero. The microcontroller
then begins program execution at location, 000000h.
The user programs a GOTO instruction at the Reset
address, which redirects program execution to the
appropriate start-up routine.
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. Refer to Section 8. “Interrupts”
(DS39707)
in
the
“PIC24F
Family
Reference Manual”
for more information.
Note:
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET
instruction.
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