參數(shù)資料
型號: PIC24FJ48GA002T-I/SO
廠商: Microchip Technology
文件頁數(shù): 31/52頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 48K 28SOIC
產(chǎn)品培訓(xùn)模塊: Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 48KB(16K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164339-ND - MODULE SKT FOR PM3 28SOIC
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
2008 Microchip Technology Inc.
DS39768D-page 37
PIC24FJXXXGA0XX
5.2.6
READC COMMAND
The READC command instructs the programming
executive to read N or Device ID registers, starting from
the 24-bit address specified by Addr_MSB and
Addr_LS. This command can only be used to read 8-bit
or 16-bit data.
When this command is used to read Device ID
registers, the upper byte in every data word returned by
the programming executive is 00h and the lower byte
contains the Device ID register value.
Expected Response (4 + 3 * (N – 1)/2 words for N odd):
1100h
2 + N
Device ID Register 1
...
Device ID Register N
5.2.7
READP COMMAND
The READP command instructs the programming
executive to read N 24-bit words of code memory,
including Configuration Words, starting from the 24-bit
address specified by Addr_MSB and Addr_LS. This
command can only be used to read 24-bit data. All data
returned in response to this command uses the packed
data format described in Section 5.2.2 “Packed Data
Expected Response (2 + 3 * N/2 words for N even):
1200h
2 + 3 * N/2
Least significant program memory word 1
...
Least significant data word N
Expected Response (4 + 3 * (N – 1)/2 words for N odd):
1200h
4 + 3 * (N – 1)/2
Least significant program memory word 1
...
MSB of program memory word N (zero padded)
15
12 11
8 7
0
Opcode
Length
NAddr_MSB
Addr_LS
Field
Description
Opcode
1h
Length
3h
N
Number of 8-bit Device ID registers to
read (max. of 256)
Addr_MSB
MSB of 24-bit source address
Addr_LS
Least Significant 16 bits of 24-bit
source address
Note:
Reading
unimplemented
memory
will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
15
12 11
8 7
0
Opcode
Length
N
Reserved
Addr_MSB
Addr_LS
Field
Description
Opcode
2h
Length
4h
N
Number of 24-bit instructions to read
(max. of 32768)
Reserved
0h
Addr_MSB
MSB of 24-bit source address
Addr_LS
Least Significant 16 bits of 24-bit
source address
Note:
Reading
unimplemented
memory
will
cause the programming executive to
reset. Please ensure that only memory
locations present on a particular device
are accessed.
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