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參數(shù)資料
| 型號： | PIC24FJ128GB110-I/PF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 100TQFP |
| 標準包裝： | 90 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SPI，UART/USART，USB OTG |
| 外圍設備： | 欠壓檢測/復位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲器容量： | 128KB（43K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 16x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 648 (CN2011-ZH PDF) |
| 配用： | 876-1004-ND - PIC24 BREAKOUT BOARD |
PIC24FJ256GB110 FAMILY
DS80369N-page 6
2008-2011 Microchip Technology Inc.
11. Module: USB
The Bus Activity Interrupt Flag, ACTVIF, is active
only while the device is in Sleep mode. It will not
become set when the microcontroller is in a Run
mode.
Work around
The type of work around depends on the type of
application that the microcontroller is being used
for.
For Self-Powered Peripherals:
After receiving a
Suspend command from the PC, do NOT suspend
or disable the USB module. In addition, do not
switch to a clock configuration that is incompatible
with USB operation (refer to the device data sheet
for USB compatible clock settings).
For Bus Powered Peripherals:
After receiving a
suspend command from the PC (IDLEIF Interrupt
Flag = 1):
Suspend the USB module (U1PWRC<1> = 1)
Globally enable USB interrupts (IEC5<6> = 1)
Specifically enable the bus activity interrupt
(U1OTGIE<4> = 1)
Place the microcontroller into Sleep mode as
soon as possible
For Embedded Host Devices:
Issue a suspend command to the peripheral
device
Suspend the USB module (U1PWRC<1> = 1)
Globally enable USB interrupts (IEC5<6> = 1)
Place the microcontroller into Sleep mode as
soon as possible
As an alternate procedure, do NOT suspend or
disable the USB module and do not switch to a
clock configuration that is incompatible with USB
operation.
Affected Silicon Revisions
12. Module: UART (UERIF Interrupt)
The UARTx error interrupt may not occur, or occur
at an incorrect time, if multiple errors occur during
a short period of time.
Work around
Read the error flags in the UxSTA register when-
ever a byte is received to verify the error status. In
most cases, these bits will be correct, even if the
UARTx error interrupt fails to occur. For possible
exceptions, refer to Errata # 13.
Affected Silicon Revisions
13. Module: UART (FIFO Error Flags)
Under certain circumstances, the PERR and
FERR error bits may not be correct for all bytes in
the receive FIFO. This has only been observed
when both of the following conditions are met:
The UARTx receive interrupt is set to occur
when the FIFO is full or full
(UxSTA<7:6> = 1x)
More than 2 bytes with an error are received
In these cases, only the first two bytes with a parity
or framing error will have the corresponding bits
indicate correctly. The error bits will not be set after
this.
Work around
None.
Affected Silicon Revisions
14. Module: UART (IrDA)
When the UARTx is operating in 8-bit mode
(PDSEL<1:0> = 0x) and using the IrDA endec
(IREN = 1), the module incorrectly transmits a
data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
A3
A5
A6
XX
X
A3
A5
A6
X
A3
A5
A6
X
A3
A5
A6
X
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