
CHAPTER 3 CPU FUNCTION
User’s Manual U15905EJ2V1UD
87
3.4.9
Notes
Be sure to set the following register first when using the V850ES/SA2 and V850ES/SA3:
System wait control register (VSWC)
After setting the VSWC register, set the other registers as necessary.
When using the external bus, initialize each register in the following order after setting the above register.
<1> Set each pin to the control mode by using the port-related registers.
(1) System wait control register (VSWC)
The system wait control register (VSWC) controls wait of bus access to the internal peripheral I/O registers.
Three clocks are required to access an internal peripheral I/O register (without a wait cycle). The V850ES/SA2
and V850ES/SA3 require wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (fCLK)
Set Value of VSWC
2 MHz
≤ fCLK < 16.6 MHz
00H
16.6 MHz
≤ fCLK ≤ 20 MHz
01H
(2) Access to special internal peripheral I/O registers
When accessing the following registers, if the CPU accesses the register at the same time the register
changes due to hardware processing, a wait operation is generated for the register access. In this case, it may
take longer to access the internal peripheral I/O registers compared with ordinary access.
Peripheral Function
Target Register Name
DMA
DTFR0 to DTFR3
Timer n (n = 0, 1)
TMn, CCn0, CCn1, TMCn0
Watchdog timer
WDTM
UARTn (n = 0, 1)
ASISn
I
2C bus
IICS
Caution
When the CPU operates on the subclock and main oscillation is stopped, access to a
register for which a wait is generated is prohibited. If a wait is generated, only reset
can release the wait.