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CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U15905EJ2V1UD
208
6.4
Operation
6.4.1
Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
CLS Bit = 0
MCK Bit = 0
CLS Bit = 1
MCK Bit = 0
CLS Bit = 1
MCK Bit = 1
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<6>
<7>
Main resonator (fX)
×
√
×
√
×
Sub-resonator (fXT)
√
CPU clock (fCPU)
×
√
×
√
×
Internal system clock (fCLK)
×
√
×
√
×
√
×
Peripheral clock (fXX to fXX/512)
×
√
×
√
×
WDT clock (fXW)
×
√
×
Note
×
RTC clock (sub)
√
RTC clock (main)
×
√
×
√
×
Note
The watchdog timer clock (fXW) is operable but it stops operating in the watchdog timer if the CLS bit of the
processor clock control register (PCC) is set to 1.
Remarks CLS bit: Bit 6 of PCC register
MCK bit: Bit 4 of PCC register
√: Operable
×: Stops
<1>: RESET pin input
<2>: During oscillation stabilization time count
<3>: HALT mode
<4>: IDLE mode
<5>: Software STOP mode
<6>: Subclock operation mode
<7>: Sub-IDLE mode
6.4.2
Clock output function
The clock output function allows the CLKOUT pin to output the internal system clock (fCLK).
The internal system clock (fCLK) is selected by using the CK3 to CK0 bits of the processor clock control register
(PCC).
The CLKOUT pin functions alternately as the PCM1 pin and operates as a clock output pin when the control
register of port CM is manipulated (refer to 4.3.9 Port CM).
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1, and can output the clock when
it is
√ (operable). When it is × (stops), it outputs a low level. Immediately after reset <1> and in the operation status of
<2>, the alternate function of the CLKOUT pin is used (PCM1: input mode), and therefore the pin goes into a high-
impedance state.