CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
User’s Manual U15905EJ2V1UD
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(b) Timer clock selection registers 4 and 5 (TCL4 and TCL5)
Falling edge of TIn
Rising edge of TIn
fXX/4
fXX/8
fXX/16
fXX/32
fXX/128
fXX/256
Count clock selection
TCLn2
0
1
TCLn1
0
1
0
1
TCLn0
0
1
0
1
0
1
0
1
20 MHz
10 MHz
200 ns
400 ns
800 ns
1.6 s
6.4 s
12.8 s
400 ns
800 ns
1.6 s
3.2 s
12.8 s
25.6 s
Clock
fXX
0
TCLn
(n = 4, 5)
0
TCLn2
TCLn1
TCLn0
After reset: 00H
R/W
Address: TCL4 FFFFF654H, TCL5 FFFFF655H
7
6
54
32
1
0
Cautions 1. Before overwriting the TCLn register with different data, stop the timer operation.
2. TI4 and TI5 are used alternately as P03/INTP3 and P04/INTP4, respectively, so when using
the TIn pin function, set the PMC03 or PMC04 bit of the PMC0 register to 1 before starting
timer operation. Edge detection may not be correctly performed if the bit is manipulated
after the timer starts operating.
Remark
When TCL4 and TCL5 are connected in cascade, the TCL5 register settings are invalid.