
User’s Manual U15905EJ2V1UD
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CHAPTER 5 BUS CONTROL FUNCTION
The V850ES/SA2 and V850ES/SA3 are provided with an external bus interface function by which external
memories such as ROM and RAM, and I/O can be connected.
5.1
Features
Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum
of 2 bus cycles.
Four-space chip select signal output function
8-bit/16-bit data bus selectable (for each area selected by chip select function)
Wait function
Programmable wait function of up to 7 states (selectable for each area selected by chip select function)
External wait function using WAIT pin
Idle state function
Bus hold function
5.2
Bus Control Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. Bus Control Pins (Multiplexed Bus)
Bus Control Pin
Alternate-Function Pin
I/O
Function
AD0 to AD15
PDL0 to PDL15
I/O
Address/data bus
A16 to A23
Note
PDH0 to PDH7
Output
Address bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
CS0 to CS3
PCS0 to PCS3
Output
Chip select signal
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
ASTB
PCT6
Output
Address strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
Bus hold control
Note
A16 to A21 in the V850ES/SA2