2001 Microchip Technology Inc.
Advance Information
DS39541A-page 313
PIC18C601/801
SSP ..................................................................................
149Block Diagram
SPI Mode .........................................................
153Block Diagram (SPI Mode) ......................................
153SPI Mode .................................................................
153SSPBUF ..................................................................
155SSPCON1 ...............................................................
151SSPCON2 ...............................................................
152SSPSR ....................................................................
155SSPSTAT ................................................................
150TMR2 Output for Clock Shift ...........................
135SSP Module
SPI Master Mode .....................................................
155SPI Slave Mode .......................................................
156SSPCON1 Register .........................................................
151SSPCON2 Register .........................................................
152SSPOV ............................................................................
167SSPSTAT Register ..........................................................
150R/W Bit ....................................................................
160SUBFWB ................................................................
250SUBLW ............................................................................
251SUBWF ............................................................................
252SUBWFB .........................................................................
253SWAPF ............................................................................
254T
Table Pointer Register .......................................................
74Table Read ........................................................................
75Table Read/Write Control Registers ..................................
74Table Write ........................................................................
7716-bit External
16-bit Word Write Mode .....................................
81Byte Select Mode ..............................................
82Byte Write Mode ................................................
808-bit External .............................................................
78Table Writes
Long Writes ...............................................................
83TBLRD .............................................................................
255TBLWT .............................................................................
256Timer0 ..............................................................................
127Associated Registers ...............................................
129Block Diagram
16-bit Mode ......................................................
1288-bit Mode ........................................................
128Clock Source Edge Select (T0SE Bit) .....................
129Clock Source Select (T0CS Bit) ..............................
129Interrupt ...................................................................
101Overflow Interrupt ....................................................
129T0CON Register ......................................................
127Timing Diagram .......................................................
281Timer1 ..............................................................................
130Associated Registers ...............................................
134Block Diagram .........................................................
13116-bit R/W Mode ..............................................
132Oscillator .........................................................
130Overflow Interrupt ...........................................
130Special Event Trigger (CCP) ...........................
133T1CON Register ......................................................
130Timing Diagram .......................................................
281TMR1H Register .....................................................
130TMR1L Register ......................................................
130TMR3L Register ......................................................
137Timer2
Associated Registers ..............................................
136Block Diagram .........................................................
136PR2 Register ...................................................
135SSP Clock Shift ...............................................
135T2CON Register ......................................................
135TMR2 Register ........................................................
135TMR2 to PR2 Match Interrupt ................
135Timer3 .............................................................................
137Associated Registers ..............................................
139Block Diagram .........................................................
13816-bit R/W Mode .............................................
138Oscillator .........................................................
137Overflow Interrupt ............................................
137Special Event Trigger (CCP) ...................................
139T3CON Register ......................................................
137TMR3H Register .....................................................
137Timing Diagrams
Acknowledge Sequence Timing ..............................
170Baud Rate Generator with Clock Arbitration ...........
165BRG Reset Due to SDA Collision ...........................
174Bus Collision
START Condition Timing ................................
173Bus Collision During a RESTART Condition
(Case 1) ..................................................
175Bus Collision During a RESTART Condition
(Case 2) ..................................................
175Bus Collision During a START Condition
(SCL = 0) .................................................
174Bus Collision During a STOP Condition ..................
176Bus Collision for Transmit and Acknowledge ..........
172I2C Bus Data ........................................................... 289 I2C Master Mode First START Bit Timing ............... 165 I2C Master Mode Reception Timing ........................ 169 I2C Master Mode Transmission Timing ................... 168 Master Mode Transmit Clock Arbitration .................
171Repeated START Condition ....................................
166Slave Synchronization .............................................
156Slow Rise Time .........................................................
33SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram .........................
155SPI Mode Timing (Slave Mode with CKE = 0) ........
157SPI Mode Timing (Slave Mode with CKE = 1) ........
157STOP Condition Receive or Transmit .....................
170Time-out Sequence on Power-up .............................
32USART Asynchronous Master Transmission ..........
184USART Asynchronous Reception ...........................
186USART Synchronous Reception .............................
189USART Synchronous Transmission ........................
188Wake-up from SLEEP via Interrupt .........................
213