PIC18FXX39
DS30485A-page 262
Preliminary
2002 Microchip Technology Inc.
IDD
Supply Current(2)
D010C
PIC18LFXX39
—10
25
mA
EC, ECIO osc configurations
VDD = 4.2V, -40
°C to +85°C
D010C
PIC18FXX39
—
10
25
mA
EC, ECIO osc configurations
VDD = 4.2V, -40
°C to +125°C
D013
PIC18LFXX39
—
10
15
25
mA
HS osc configuration
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
D013
PIC18FXX39
—
10
15
25
mA
HS osc configuration
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
IPD
Power-down Current(3)
D020
PIC18LFXX39
—
0.08
0.1
3
0.9
4
10
A
VDD = 2.0V, +25
°C
VDD = 2.0V, -40
°C to +85°C
VDD = 4.2V, -40
°C to +85°C
D020
D021B
PIC18FXX39
—
.1
3
15
.9
10
25
A
VDD = 4.2V, +25
°C
VDD = 4.2V, -40
°C to +85°C
VDD = 4.2V, -40
°C to +125°C
23.1
DC Characteristics: PIC18FXX39 (Industrial, Extended)
PIC18LFXX39 (Industrial) (Continued)
PIC18LFXX39
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
≤ TA ≤ +85°C for industrial
PIC18FXX39
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C
≤ TA ≤ +85°C for industrial
-40°C
≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all
features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
4: The LVD and BOR modules share a large portion of circuitry. The
IBOR and ILVD currents are not additive.
Once one of these modules is enabled, the other may also be enabled without further penalty.