參數(shù)資料
型號： PIC18LF452-I/P
廠商： Microchip Technology
文件頁數(shù)： 97/134頁
文件大?。?/td> 0K
描述： IC MCU FLASH 16KX16 A/D 40DIP
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 10
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
1997 Microchip Technology Inc.
DS30444E - page 65
PIC16C9XX
11.1
SPI Mode
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO) RC5/SDO
Serial Data In (SDI) RC4/SDI
Serial Clock (SCK) RC3/SCK
Additionally a fourth pin may be used when in a slave
mode of operation:
Slave Select (SS) RA5/AN4/SS (the AN4 function
is implemented on the PIC16C924 only)
When initializing the SPI, several options need to be
specied. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specied:
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
Clock Rate (Master mode only)
Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb rst. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register.
Then
the
buffer
full
detect
bit
BF
(SSPSTAT<0>) and interrupt ag bit SSPIF (PIR1<3>)
are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit WCOL
(SSPCON<7>) will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed success-
fully. When the application software is expecting to
receive valid data, the SSPBUF should be read before
the next byte of data to transfer is written to the
SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
bit BF is cleared. This data may be irrelevant if the SPI
is only a transmitter. Generally the SSP Interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or writ-
ten. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write col-
lision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) for data transmission. The
shaded instruction is only required if the received data
is meaningful.
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
BCF
STATUS, RP1
;Select Bank1
BSF
STATUS, RP0
;
LOOP BTFSS SSPSTAT, BF
;Has data been
;received
;(transmit
;complete)?
GOTO
LOOP
;No
BCF
STATUS, RP0
;Select Bank0
MOVF
SSPBUF, W
;W reg = contents
; of SSPBUF
MOVF
TXDATA, W
;W reg = contents
; of TXDATA
MOVWF SSPBUF
;New data to xmit
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
MOVWF RXDATA
;Save in user RAM
Read
Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/AN4/SS
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
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