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參數(shù)資料
| 型號： | PIC18LF44J50-I/ML |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 16K 2V 44-QFN |
| 產(chǎn)品培訓(xùn)模塊： | XLP Deep Sleep Mode 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，SPI，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 16KB（8K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-VQFN 裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 656 (CN2011-ZH PDF) |
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2009 Microchip Technology Inc.
DS39687E-page 7
PIC18F2XJXX/4XJXX FAMILY
2.3
Overview of the Programming
Process
Figure 2-5 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory is programmed. Since the only
nonvolatile Configuration Words are within the code
memory space, they too are programmed as if they
were code. Code memory (including the Configuration
Words) is then verified to ensure that programming was
successful.
FIGURE 2-5:
HIGH-LEVEL
PROGRAMMING FLOW
2.4
Entering and Exiting ICSP
Program/Verify Mode
Entry into ICSP modes for PIC18F2XJXX/4XJXX family
devices is somewhat different than previous PIC18
devices. As shown in Figure 2-6, entering ICSP
Program/Verify mode requires three steps:
1.
Voltage is briefly applied to the MCLR pin.
2.
A 32-bit key sequence is presented on PGD.
3.
Voltage is reapplied to MCLR and held.
The programming voltage applied to MCLR is VIH, or
essentially, VDD. There is no minimum time requirement
for holding at VIH. After VIH is removed, an interval of at
least P19 must elapse before presenting the key
sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 4D434850h in hexa-
decimal). The device will enter Program/Verify mode
only if the sequence is valid. The Most Significant bit of
the most significant nibble must be shifted in first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time, P20 and P12, must elapse before present-
ing data on PGD. Signals appearing on PGD before P12
has elapsed may not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
Exiting Program/Verify mode is done by removing VIH
from MCLR, as shown in Figure 2-7. The only require-
ment for exit is that an interval, P16, should elapse
between the last clock and program signals on PGC
and PGD before removing VIH.
When VIH is reapplied to MCLR, the device will enter
the ordinary operational mode and begin executing the
application instructions.
FIGURE 2-6:
ENTERING PROGRAM/VERIFY MODE
Start
Done
Perform Bulk
Erase
Program Memory
Verify Program
Done
Enter ICSP
Exit ICSP
MCLR
PGD
PGC
VDD
P13
b31
b30 b29
b28
b27
b2
b1
b0
b3
...
Program/Verify Entry Code = 4D434850h
P2B
P2A
P19
P20
0
1
001
000
0
P12
VIH
P1
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