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    參數(shù)資料
    型號: PIC18LF4321-I/ML
    廠商: Microchip Technology
    文件頁數(shù): 82/110頁
    文件大小: 0K
    描述: IC PIC MCU FLASH 4KX16 44QFN
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標準包裝: 45
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 40MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
    輸入/輸出數(shù): 36
    程序存儲器容量: 8KB(4K x 16)
    程序存儲器類型: 閃存
    EEPROM 大小: 256 x 8
    RAM 容量: 512 x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-VQFN 裸露焊盤
    包裝: 管件
    產(chǎn)品目錄頁面: 642 (CN2011-ZH PDF)
    2009 Microchip Technology Inc.
    DS39689F-page 73
    PIC18F2221/2321/4221/4321 FAMILY
    6.4
    Data Addressing Modes
    The data memory space can be addressed in several
    ways. For most instructions, the addressing mode is
    fixed. Other instructions may use up to three modes,
    depending on which operands are used and whether or
    not the extended instruction set is enabled.
    The addressing modes are:
    Inherent
    Literal
    Direct
    Indirect
    An additional addressing mode, Indexed Literal Offset,
    is available when the extended instruction set is
    enabled (XINST Configuration bit = 1). Its operation is
    discussed in greater detail in Section 6.5.1 “Indexed
    6.4.1
    INHERENT AND LITERAL
    ADDRESSING
    Many PIC18 control instructions do not need any
    argument at all; they either perform an operation that
    globally affects the device or they operate implicitly on
    one register. This addressing mode is known as Inherent
    Addressing. Examples include SLEEP, RESET and DAW.
    Other instructions work in a similar way but require an
    additional explicit argument in the opcode. This is
    known as Literal Addressing mode because they
    require some literal value as an argument. Examples
    include ADDLW and MOVLW, which respectively, add or
    move a literal value to the W register. Other examples
    include CALL and GOTO, which include a 20-bit
    program memory address.
    6.4.2
    DIRECT ADDRESSING
    Direct addressing specifies all or part of the source
    and/or destination address of the operation within the
    opcode itself. The options are specified by the
    arguments accompanying the instruction.
    In the core PIC18 instruction set, bit-oriented and byte-
    oriented instructions use some version of direct
    addressing by default. All of these instructions include
    some 8-bit literal address as their Least Significant
    Byte. This address specifies either a register address in
    one of the banks of data RAM (Section 6.3.3 “General
    Purpose Register File”) or a location in the Access
    source for the instruction.
    The Access RAM bit ‘a(chǎn)’ determines how the address is
    interpreted. When ‘a(chǎn)’ is ‘1’, the contents of the BSR
    used with the address to determine the complete 12-bit
    address of the register. When ‘a(chǎn)’ is ‘0’, the address is
    interpreted as being a register in the Access Bank.
    Addressing that uses the Access RAM is sometimes
    also known as Direct Forced Addressing mode.
    A few instructions, such as MOVFF, include the entire
    12-bit address (either source or destination) in their
    opcodes. In these cases, the BSR is ignored entirely.
    The destination of the operation’s results is determined
    by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
    stored back in the source register, overwriting its origi-
    nal contents. When ‘d’ is ‘0’, the results are stored in
    the W register. Instructions without the ‘d’ argument
    have a destination that is implicit in the instruction; their
    destination is either the target register being operated
    on or the W register.
    6.4.3
    INDIRECT ADDRESSING
    Indirect addressing allows the user to access a location
    in data memory without giving a fixed address in the
    instruction. This is done by using File Select Registers
    (FSRs) as pointers to the locations to be read or written
    to. Since the FSRs are themselves located in RAM as
    Special Function Registers, they can also be directly
    manipulated under program control. This makes FSRs
    very useful in implementing data structures, such as
    tables and arrays in data memory.
    The registers for indirect addressing are also
    implemented with Indirect File Operands (INDFs) that
    permit automatic manipulation of the pointer value with
    auto-incrementing, auto-decrementing or offsetting
    with another value. This allows for efficient code, using
    loops, such as the example of clearing an entire RAM
    bank in Example 6-5.
    EXAMPLE 6-5:
    HOW TO CLEAR RAM
    (BANK 1) USING
    INDIRECT ADDRESSING
    Note:
    The execution of some instructions in the
    core PIC18 instruction set are changed
    when the PIC18 extended instruction set is
    more information.
    LFSR
    FSR0, 100h ;
    NEXT
    CLRF
    POSTINC0
    ; Clear INDF
    ; register then
    ; inc pointer
    BTFSS
    FSR0H, 1
    ; All done with
    ; Bank1?
    BRA
    NEXT
    ; NO, clear next
    CONTINUE
    ; YES, continue
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