參數(shù)資料
型號: PIC18LF258-I/SO
廠商: Microchip Technology
文件頁數(shù): 9/116頁
文件大?。?/td> 0K
描述: IC MCU CAN FLASH 16K LP 28-SOIC
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
PIC18FXX8
DS41159E-page 104
2006 Microchip Technology Inc.
9.5
PORTE, TRISE and LATE
Registers
PORTE is a 3-bit wide, bidirectional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corre-
sponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
The TRISE register also controls the operation of the
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
PORTE pins are also multiplexed with inputs for the A/D
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE<2:0> control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
EXAMPLE 9-5:
INITIALIZING PORTE
FIGURE 9-10:
PORTE BLOCK DIAGRAM
Note:
This
port
is
only
available
on
the
PIC18F448 and PIC18F458.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
03h
; Value used to
; initialize data
; direction
MOVWF
TRISE
; Set RE1:RE0 as inputs
; RE2 as an output
; (RE4=0 - PSPMODE Off)
Peripheral Out Select
Data Bus
WR LATE
WR TRISE
Data
Latch
TRIS Latch
RD TRISE
Q
D
Q
CK
QD
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
VDD
VSS
RD PORTE
Peripheral Data In
I/O pin(1)
or
WR PORTE
RD LATE
Schmitt
Trigger
Note
1: I/O pins have diode protection to VDD and VSS.
TRIS OVERRIDE
Pin
Override Peripheral
RE0
Yes
PSP
RE1
Yes
PSP
RE2
Yes
PSP
TRIS
Override
Peripheral Enable
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