
PIC18F2X1X/4X1X
DS39636C-page 288
Preliminary
2007 Microchip Technology Inc.
RETFIE
Example:
RETLW
Example:
Return from Interrupt
Syntax:
RETFIE {s}
Operands:
s
∈
[0,1]
(TOS)
→
PC,
1
→
GIE/GIEH or PEIE/GIEL,
if s =
1
(WS)
→
W,
(STATUSS)
→
STATUS,
(BSRS)
→
BSR,
PCLATU, PCLATH are unchanged.
Operation:
Status Affected:
GIE/GIEH, PEIE/GIEL.
Encoding:
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low priority
global interrupt enable bit. If ‘s’ =
1
, the
contents of the shadow registers WS,
STATUSS and BSRS are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ =
0
, no update
of these registers occurs (default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
No
Q3
No
Q4
Decode
operation
operation
POP PC
from stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
RETFIE 1
After Interrupt
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
Return Literal to W
Syntax:
RETLW k
Operands:
0
≤
k
≤
255
k
→
W,
(TOS)
→
PC,
PCLATU, PCLATH are unchanged
Operation:
Status Affected:
None
Encoding:
0000
1100
kkkk
kkkk
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
:
TABLE
CALL TABLE ; W contains table
; offset value
; W now has
; table value
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
; W = offset
; Begin table
;
; End of table
Before Instruction
W
After Instruction
W
=
07h
=
value of kn