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2007 Microchip Technology Inc.
Preliminary
DS39636C-page 371
PIC18F2X1X/4X1X
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) ....................................148
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) .....................................148
PWM Direction Change ...........................................145
PWM Direction Change at Near
100% Duty Cycle .............................................145
PWM Output ............................................................134
Repeat Start Condition .............................................180
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ...........334
Send Break Character Sequence ............................205
Slave Synchronization .............................................157
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
) ............................................47
SPI Mode (Master Mode) .........................................156
SPI Mode (Slave Mode, CKE = 0) ...........................158
SPI Mode (Slave Mode, CKE = 1) ...........................158
Synchronous Reception (Master Mode, SREN) ......208
Synchronous Transmission ......................................206
Synchronous Transmission (Through TXEN) ..........207
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
) ...........................................47
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
, Case 1) .......................46
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
, Case 2) .......................46
Time-out Sequence on Power-up
(MCLR Tied to V
DD
, V
DD
Rise < T
PWRT
) ...........46
Timer0 and Timer1 External Clock ..........................335
Transition for Entry to Idle Mode ................................38
Transition for Entry to SEC_RUN Mode ....................35
Transition for Entry to Sleep Mode ............................37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................248
Transition for Wake from Idle to Run Mode ...............38
Transition for Wake from Sleep (HSPLL) ...................37
Transition from RC_RUN Mode to
PRI_RUN Mode .................................................36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ..................................35
Transition to RC_RUN Mode .....................................36
USART Synchronous Receive (Master/Slave) ........346
USART Synchronous Transmission
(Master/Slave) .................................................346
Timing Diagrams and Specifications ................................331
A/D Conversion Requirements ................................348
Capture/Compare/PWM (CCP)
Requirements ..................................................336
CLKO and I/O Requirements ...................................333
Example SPI Mode Requirements
(Master Mode, CKE = 0) ..................................338
Example SPI Mode Requirements
(Master Mode, CKE = 1) ..................................339
Example SPI Mode Requirements
(Slave Mode, CKE = 0) ....................................340
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 341
External Clock Requirements .................................. 331
I
2
C Bus Data Requirements (Slave Mode) .............. 343
Master SSP I
2
C Bus Data Requirements ................ 345
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 344
Parallel Slave Port Requirements
(PIC18F4410/4510/4515/4610) ....................... 337
PLL Clock ................................................................ 332
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 334
Timer0 and Timer1 External Clock
Requirements .................................................. 335
USART Synchronous Receive Requirements ......... 346
USART Synchronous Transmission
Requirements .................................................. 346
Top-of-Stack Access .......................................................... 54
TRISE Register
PSPMODE Bit ......................................................... 104
TSTFSZ ........................................................................... 297
Two-Speed Start-up ................................................. 237, 248
Two-Word Instructions
Example Cases ......................................................... 58
TXSTA Register
BRGH Bit ................................................................. 195
V
Voltage Reference Specifications .................................... 327
W
Watchdog Timer (WDT) ........................................... 237, 246
Associated Registers ............................................... 247
Control Register ....................................................... 246
During Oscillator Failure .......................................... 249
Programming Considerations .................................. 246
WCOL ...................................................... 179, 180, 181, 184
WCOL Status Flag ................................... 179, 180, 181, 184
WWW Address ................................................................ 373
WWW, On-Line Support ...................................................... 6
X
XORLW ........................................................................... 297
XORWF ........................................................................... 298