參數(shù)資料
型號: PIC18LF2321-I/SO
廠商: Microchip Technology
文件頁數(shù): 53/110頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 27
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 642 (CN2011-ZH PDF)
2009 Microchip Technology Inc.
DS39689F-page 47
PIC18F2221/2321/4221/4321 FAMILY
5.0
RESET
The
PIC18F2221/2321/4221/4321
family
devices
differentiate between various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog Timer (WDT) Reset (during
execution)
e)
Programmable Brown-out Reset (BOR)
f)
RESET Instruction
g)
Stack Full Reset
h)
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in Section 24.2 “Watchdog
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.6 “Reset State
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
11-Bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 5-2 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32
μs
MCLRE
S
R
Q
Chip_Reset
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