2006 Microchip Technology Inc.
Advance Information
DS39762A-page 83
PIC18F97J60 FAMILY
T3CON
PSPCON
(5)
RD16
T3CCP2
T3CKPS1
T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
60, 175
IBF
OBF
IBOV
PSPMODE
—
—
—
—
0000 ----
61, 161
SPBRG1
EUSART1 Baud Rate Generator Register Low Byte
0000 0000
61, 306
RCREG1
EUSART1 Receive Register
0000 0000
61, 313
TXREG1
EUSART1 Transmit Register
xxxx xxxx
61, 315
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010
61, 306
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
61, 306
EECON2
Program Memory Control Register (not a physical register)
---- ----
61, 96
EECON1
—
—
—
FREE
TX2IP
(6)
TX2IF
(6)
TX2IE
(6)
WRERR
WREN
WR
—
---0 x00-
61, 97
IPR3
SSP2IP
(5)
SSP2IF
(5)
SSP2IE
(5)
BCL2IP
(5)
BCL2IF
(5)
BCL2IE
(5)
RC2IP
(6)
RC2IF
(6)
RC2IE
(6)
TMR4IP
CCP5IP
CCP4IP
CCP3IP
1111 1111
61, 132
PIR3
TMR4IF
CCP5IF
CCP4IF
CCP3IF
0000 0000
61, 126
PIE3
TMR4IE
CCP5IE
CCP4IE
CCP3IE
0000 0000
61, 129
IPR2
OSCFIP
CMIP
ETHIP
r
BCL1IP
—
TMR3IP
CCP2IP
1111 1-11
61, 131
PIR2
OSCFIF
CMIF
ETHIF
r
BCL1IF
—
TMR3IF
CCP2IF
0000 0-00
61, 125
PIE2
OSCFIE
PSPIP
(9)
PSPIF
(9)
PSPIE
(9)
CMIE
ETHIE
r
BCL1IE
—
TMR3IE
CCP2IE
0000 0-00
61, 128
IPR1
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
1111 1111
61, 130
PIR1
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000
61, 124
PIE1
MEMCON
(5,7)
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000
61, 127
EBDIS
—
WAIT1
WAIT0
—
—
WM1
WM0
0-00 --00
61, 106
OSCTUNE
TRISJ
(6)
TRISH
(6)
PPST1
TRISJ7
(5)
TRISH7
(6)
TRISG7
(5)
PLLEN
(8)
TRISJ6
(5)
TRISH6
(6)
TRISG6
(5)
PPST0
TRISJ5
(5)
TRISH5
(6)
TRISG5
(5)
PPRE
TRISJ4
(5)
TRISH4
(6)
—
—
—
—
0000 ----
61, 41
TRISJ3
(5)
TRISH3
(6)
TRISG3
(6)
TRISJ2
(5)
TRISH2
(6)
TRISG2
(6)
TRISJ1
(5)
TRISH1
(6)
TRISG1
(6)
TRISJ0
(5)
TRISH0
(6)
TRISG0
(6)
TRISF0
(5)
1111 1111
61, 159
1111 1111
61, 157
TRISG
TRISG4
1111 1111
61, 155
TRISF
TRISF7
TRISE7
(6)
TRISD7
(5)
TRISF6
TRISE6
(6)
TRISD6
(5)
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
1111 1111
61, 152
TRISE
TRISE5
TRISD5
(5)
TRISE4
TRISD4
(5)
TRISE3
TRISD3
(5)
TRISE2
TRISE1
TRISE0
1111 1111
61, 150
TRISD
TRISD2
TRISD1
TRISD0
1111 1111
61, 147
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
61, 143
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
61, 140
TRISA
LATJ
(6)
LATH
(6)
—
—
TRISA5
LATJ5
(6)
LATH5
(6)
LATG5
(5)
TRISA4
LATJ4
(6)
LATH4
(6)
TRISA3
LATJ3
(5)
LATH3
(6)
LATG3
(6)
TRISA2
LATJ2
(5)
LATH2
(6)
LATG2
(6)
TRISA1
LATJ1
(5)
LATH1
(6)
LATG1
(6)
TRISA0
LATJ0
(5)
LATH0
(6)
LATG0
(6)
LATF0
(5)
--11 1111
61, 137
LATJ7
(5)
LATH7
(6)
LATG7
(5)
LATJ6
(5)
LATH6
(6)
LATG6
(5)
xxxx xxxx
61, 159
xxxx xxxx
61, 157
LATG
LATG4
xxxx xxxx
62, 155
LATF
LATF7
LATE7
(6)
LATD7
(5)
LATF6
LATE6
(6)
LATD6
(5)
LATF5
LATF4
LATF3
LATF2
LATF1
xxxx xxxx
62, 152
LATE
LATE5
LATD5
(5)
LATE4
LATD4
(5)
LATE3
LATD3
(5)
LATE2
LATE1
LATE0
xxxx xxxx
62, 150
LATD
LATD2
LATD1
LATD0
xxxx xxxx
62, 147
LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
xxxx xxxx
62, 143
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx xxxx
62, 140
LATA
PORTJ
(6)
PORTH
(6)
RDPU
RJ7
(5)
RH7
(6)
RG7
(5)
REPU
RJ6
(5)
RH6
(6)
RG6
(5)
LATA5
RJ5
(6)
RH5
(6)
RG5
(5)
LATA4
RJ4
(6)
RH4
(6)
LATA3
RJ3
(5)
RH3
(6)
RG3
(6)
LATA2
RJ2
(5)
RH2
(6)
RG2
(6)
LATA1
RJ1
(5)
RH1
(6)
RG1
(6)
LATA0
RJ0
(5)
RH0
(6)
RG0
(6)
00xx xxxx
62, 137
xxxx xxxx
62, 159
0000 xxxx
62, 157
PORTG
RG4
111x xxxx
62, 155
TABLE 5-5:
REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Values on
POR, BOR
Details on
page:
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented, read as ‘
0
’,
q
= value depends on condition, r = reserved bit, do not modify. Shaded cells
are unimplemented, read as ‘
0
’.
Note 1:
Bit 7 and bit 6 are cleared by user software or by a POR.
2:
Bit 21 of the PC is only available in Serial Programming modes.
3:
Reset value is ‘
0
’ when Two-Speed Start-up is enabled and ‘
1
’ if disabled.
4:
Alternate names and definitions for these bits when the MSSP module is operating in I
2
C Slave mode.
5:
These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ‘
0
’. Reset values shown
apply only to 100-pin devices.
6:
These bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and read as ‘
0
’. Reset
values are shown for 100-pin devices.
7:
In Microcontroller mode, the bits in this register are unwritable and read as ‘
0
’.
8:
PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as ‘
0
’.
9:
Implemented in 100-pin devices in Microcontroller mode only.