
2007 Microchip Technology Inc.
Preliminary
DS39778B-page 57
PIC18F87J11 FAMILY
ADRESH
ADRESL
ADCON0
ADCON1
ANCON0
ANCON1
WDTCON
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
ECCP2AS
ECCP2DEL
CCPR2H
CCPR2L
CCP2CON
ECCP3AS
ECCP3DEL
CCPR3H
CCPR3L
CCP3CON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
Legend:
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
PIC18F6XJ1X PIC18F8XJ1X
u
= unchanged,
x
= unknown,
-
= unimplemented bit, read as ‘
0
’,
q
= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h
or
0018h).
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
See Table 4-1 for Reset value for specific condition.
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
00-0 0000
0000 0000
uu-u uuuu
uuuu uuuu
uu-u uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0x-0 ---0
0000 0000
0x-u ---0
0000 0000
ux-u ---u
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
xxxx xxxx
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
xxxx xxxx
0000 0010
uuuu uuuu
0000 0010
uuuu uuuu
uuuu uuuu
0000 000x
0000 000x
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0010
---- ----
0000 0010
---- ----
uuuu uuuu
---- ----
--00 x00-
--00 u00-
--00 u00-
TABLE 4-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets,
CM Resets
Wake-up via WDT
or Interrupt
Note 1:
2:
3:
4: