
 2004 Microchip Technology Inc.
Preliminary
DS39646B-page 25
PIC18F8722 FAMILY
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
AD0
PSP0
72
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
RD1/AD1/PSP1
RD1
AD1
PSP1
69
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
RD2/AD2/PSP2
RD2
AD2
PSP2
68
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
RD3/AD3/PSP3
RD3
AD3
PSP3
67
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
66
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
AD5
PSP5
SDI2
SDA2
65
I/O
I/O
I/O
I
I/O
ST
TTL
TTL
ST
I
2
C/SMB
Digital I/O.
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I
2
C data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
AD6
PSP6
SCK2
SCL2
64
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
I
2
C/SMB
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
Legend:
63
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Slave Port data.
SPI slave select input.
CMOS
=  CMOS compatible input or output 
Analog
=  Analog input 
O
=  Output 
I
2
C/SMB =  I
2
C/SMBus input buffer 
TABLE 1-4:
PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS (CONTINUED) 
Pin Number
Pin
Type
Type
TQFP
Pin Name
Buffer
Description
TTL =  TTL compatible input 
ST
=  Schmitt Trigger input with CMOS levels 
I
=  Input 
P
=  Power 
Alternate assignment for ECCP2 when configuration bit CCP2MX is cleared (all operating modes except 
Microcontroller mode).
Default assignment for ECCP2 in all operating modes (CCP2MX is set). 
Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
Note 1:
2:
3:
4:
5: